Searched refs:control_reg0 (Results 1 – 7 of 7) sorted by relevance
| /SCP-firmware-master/product/morello/scp_ramfw_soc/ |
| A D | config_morello_pll.c | 24 .control_reg0 = (void *)SCP_PLL_CPU0_CTRL,
33 .control_reg0 = (void *)SCP_PLL_CPU1_CTRL,
42 .control_reg0 = (void *)SCP_PLL_CLUS_CTRL,
51 .control_reg0 = (void *)SCP_PLL_INTERCONNECT_CTRL,
60 .control_reg0 = (void *)SCP_PLL_SYSPLL_CTRL,
69 .control_reg0 = (void *)SCP_PLL_DMC_CTRL,
78 .control_reg0 = (void *)SCP_PLL_GPU_CTRL,
87 .control_reg0 = (void *)SCP_PLL_DPU_CTRL,
96 .control_reg0 = (void *)SCP_PLL_PIXEL_CTRL,
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| /SCP-firmware-master/product/n1sdp/scp_ramfw/ |
| A D | config_n1sdp_pll.c | 23 .control_reg0 = (void *)SCP_PLL_CPU0_CTRL,
32 .control_reg0 = (void *)SCP_PLL_CPU1_CTRL,
41 .control_reg0 = (void *)SCP_PLL_CLUS_CTRL,
50 .control_reg0 = (void *)SCP_PLL_INTERCONNECT_CTRL,
59 .control_reg0 = (void *)SCP_PLL_SYSPLL_CTRL,
68 .control_reg0 = (void *)SCP_PLL_DMC_CTRL,
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| /SCP-firmware-master/product/morello/scp_ramfw_fvp/ |
| A D | config_morello_pll.c | 24 .control_reg0 = (void *)SCP_PLL_CPU0_CTRL,
34 .control_reg0 = (void *)SCP_PLL_CPU1_CTRL,
44 .control_reg0 = (void *)SCP_PLL_CLUS_CTRL,
54 .control_reg0 = (void *)SCP_PLL_INTERCONNECT_CTRL,
64 .control_reg0 = (void *)SCP_PLL_SYSPLL_CTRL,
74 .control_reg0 = (void *)SCP_PLL_DMC_CTRL,
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| /SCP-firmware-master/product/morello/module/morello_pll/include/ |
| A D | mod_morello_pll.h | 42 volatile uint32_t *const control_reg0; member
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| /SCP-firmware-master/product/n1sdp/module/n1sdp_pll/include/ |
| A D | mod_n1sdp_pll.h | 42 volatile uint32_t * const control_reg0; member
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| /SCP-firmware-master/product/morello/module/morello_pll/src/ |
| A D | mod_morello_pll.c | 156 *config->control_reg0 = in pll_set_rate()
162 *config->control_reg0 |= (UINT32_C(1) << PLL_PLLEN_POS); in pll_set_rate()
358 if ((ctx->config->control_reg0 == NULL) || in morello_pll_element_init()
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| /SCP-firmware-master/product/n1sdp/module/n1sdp_pll/src/ |
| A D | mod_n1sdp_pll.c | 139 *config->control_reg0 = (fbdiv << PLL_FBDIV_BIT_POS) | in pll_set_rate()
145 *config->control_reg0 |= (UINT32_C(1) << PLL_PLLEN_POS); in pll_set_rate()
333 if ((ctx->config->control_reg0 == NULL) || in n1sdp_pll_element_init()
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