1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef JUNO_CLOCK_H
9 #define JUNO_CLOCK_H
10 
11 #include "juno_scc.h"
12 
13 #include <fwk_attributes.h>
14 #include <fwk_macros.h>
15 
16 #include <stdint.h>
17 
18 /* Number of entries of the HDLCD lookup table */
19 #define JUNO_CLOCK_HDLCD_LOOKUP_COUNT 566
20 /*
21  * Number of entries of the HDLCD lookup table if the HIGH_PXLCLK_ENABLE option
22  * is set.
23  */
24 #define JUNO_CLOCK_HDLCD_LOOKUP_HIGH_PXCLK_ENABLE_COUNT 746
25 
26 /* Juno clock indices */
27 enum juno_clock_idx {
28     JUNO_CLOCK_IDX_I2SCLK,
29     JUNO_CLOCK_IDX_HDLCDREFCLK,
30     JUNO_CLOCK_IDX_HDLCDPXL,
31     JUNO_CLOCK_IDX_HDLCD0,
32     JUNO_CLOCK_IDX_HDLCD1,
33     JUNO_CLOCK_IDX_BIGCLK,
34     JUNO_CLOCK_IDX_LITTLECLK,
35     JUNO_CLOCK_IDX_GPUCLK,
36     JUNO_CLOCK_IDX_COUNT
37 };
38 
39 /* Juno CDCEL937 clock indices */
40 enum juno_clock_cdcel937_idx {
41     /*
42      * Generated clocks:
43      * These clocks are generated through this driver.
44      */
45     JUNO_CLOCK_CDCEL937_IDX_I2SCLK,
46     JUNO_CLOCK_CDCEL937_IDX_HDLCDREFCLK,
47     JUNO_CLOCK_CDCEL937_IDX_HDLCDPXL,
48 
49     /*
50      * Derived clocks:
51      * These clocks are used only as reference for
52      * the HDLCD module acting as a HAL.
53      */
54     JUNO_CLOCK_CDCEL937_IDX_HDLCD0,
55     JUNO_CLOCK_CDCEL937_IDX_HDLCD1,
56 
57     /* Number of CDCEL clocks */
58     JUNO_CLOCK_CDCEL937_IDX_COUNT
59 };
60 
61 /* Juno HDLCD clock indices */
62 enum juno_clock_hdlcd_idx {
63     JUNO_CLOCK_HDLCD_IDX_HDLCD0,
64     JUNO_CLOCK_HDLCD_IDX_HDLCD1,
65     JUNO_CLOCK_HDLCD_IDX_COUNT
66 };
67 
68 /* Juno SOC clock indices for the RAM firmware */
69 enum juno_clock_soc_ram_idx {
70     JUNO_CLOCK_SOC_RAM_IDX_BIGCLK,
71     JUNO_CLOCK_SOC_RAM_IDX_LITTLECLK,
72     JUNO_CLOCK_SOC_RAM_IDX_GPUCLK,
73     JUNO_CLOCK_SOC_RAM_IDX_COUNT
74 };
75 
76 struct FWK_PACKED juno_clock_preset {
77     /*
78      * \brief Denominator value
79      *
80      * \note This value should be between 1 and 511
81      */
82     uint16_t M;
83     /*
84      * \brief Numerator value
85      *
86      * \note This value should be between 1 and 4095
87      */
88     uint16_t N;
89     /*
90      * \brief Output divider
91      *
92      * \note This value should be between 1 and 127
93      */
94     uint16_t PDIV;
95 };
96 
97 struct juno_clock_lookup {
98     struct pll_reg pll;
99     uint32_t rate_hz;
100     struct juno_clock_preset preset;
101     /*! Reserved to keep the structure 32-bit aligned */
102     uint8_t RESERVED[2];
103 };
104 
105 struct juno_clock_hdlcd_lookup {
106     uint32_t SIGNATURE_A;
107     struct juno_clock_lookup CLK[JUNO_CLOCK_HDLCD_LOOKUP_COUNT];
108     uint8_t RESERVED[24];
109     uint32_t SIGNATURE_B;
110 };
111 
112 struct juno_clock_hdlcd_lookup_high_pxlclk_enable {
113     uint32_t SIGNATURE_A;
114     struct juno_clock_lookup
115         CLK[JUNO_CLOCK_HDLCD_LOOKUP_HIGH_PXCLK_ENABLE_COUNT];
116     uint8_t RESERVED[24];
117     uint32_t SIGNATURE_B;
118 };
119 
120 #endif /* JUNO_CLOCK_H */
121