/SCP-firmware-master/product/optee-stm32mp1/module/stm32_pmic_regu/src/ |
A D | mod_stm32_pmic_regu.c | 223 int32_t *min, int32_t *max) in find_bound_uv() argument 227 fwk_assert((count == 0 || levels != NULL) && min != NULL && max != NULL); in find_bound_uv() 230 *max = INT32_MIN; in find_bound_uv() 236 if (*max < levels[n]) { in find_bound_uv() 237 *max = levels[n]; in find_bound_uv() 243 *max *= 1000; in find_bound_uv()
|
/SCP-firmware-master/module/optee/clock/src/ |
A D | mod_optee_clock.c | 186 range->max = 0; in get_range() 195 range->max = range->min; in get_range() 204 range->max = 0; in get_range() 212 if (rate > range->max) { in get_range() 213 range->max = rate; in get_range()
|
/SCP-firmware-master/product/rcar/module/rcar_clock/src/ |
A D | mod_rcar_clock.c | 535 mult = max(mult, 90U); /* Lowest value is 1.5GHz (stc == 90) */ in pll0_clk_round_rate() 568 stc_val = max(stc_val, 90U); /* Lowest value is 1.5GHz (stc == 90) */ in pll0_clk_set_rate() 592 mult = max(mult, 72U); /* Lowest value is 1.2GHz (stc == 72) */ in pll2_clk_round_rate() 625 stc_val = max(stc_val, 72U); /* Lowest value is 1.2GHz (stc == 72) */ in pll2_clk_set_rate() 657 mult = max(mult, 1U); in z_clk_round_rate() 698 mult = max(mult, 1U); in z_clk_set_rate() 754 mult = max(mult, 1U); in z2_clk_round_rate() 794 mult = max(mult, 1U); in z2_clk_set_rate()
|
/SCP-firmware-master/product/rcar/module/rcar_clock/include/ |
A D | mod_rcar_clock.h | 352 #define max(x, y) \ macro 359 #define clamp(val, lo, hi) min((__typeof__(val))max(val, lo), hi)
|
/SCP-firmware-master/module/scmi_perf/src/ |
A D | perf_plugins_handler.c | 51 uint32_t max; member 99 static inline bool are_limits_valid(uint32_t min, uint32_t max) in are_limits_valid() argument 101 return (max > min); in are_limits_valid() 216 dev_ctx->max = level_table[phy_dom]; in plugins_policy_sync_level_limits() 249 fc_update->level = dev_ctx->max; in plugins_policy_update() 486 fc_update->level = dev_ctx->max; in perf_plugins_handler_get()
|
/SCP-firmware-master/product/morello/module/dmc_bing/src/ |
A D | morello_ddr_phy.c | 53 uint16_t max; member 341 best_wrdq_eyes[slice][bit].max = DELAY_MIN; in write_eye_detect_single_rank() 396 wrdq_eyes[slice][bit].max = DELAY_MIN; in write_eye_detect_single_rank() 512 wrdq_eyes[slice][bit].max) { in write_eye_detect_single_rank() 513 wrdq_eyes[slice][bit].max = in write_eye_detect_single_rank() 524 (wrdq_eyes[slice][bit].max != DELAY_MIN)) { in write_eye_detect_single_rank() 546 eye->width = eye->max - eye->min; in write_eye_detect_single_rank() 551 eye->mid = (eye->min + eye->max) / 2; in write_eye_detect_single_rank() 596 if (eye->max == 0) { in write_eye_detect_single_rank()
|
/SCP-firmware-master/product/n1sdp/module/n1sdp_ddr_phy/src/ |
A D | mod_n1sdp_ddr_phy.c | 39 uint16_t max; member 413 best_wrdq_eyes[slice][bit].max = DELAY_MIN; in write_eye_detect_single_rank() 470 wrdq_eyes[slice][bit].max = DELAY_MIN; in write_eye_detect_single_rank() 589 wrdq_eyes[slice][bit].max) { in write_eye_detect_single_rank() 590 wrdq_eyes[slice][bit].max = in write_eye_detect_single_rank() 601 (wrdq_eyes[slice][bit].max != DELAY_MIN)) { in write_eye_detect_single_rank() 623 eye->width = eye->max - eye->min; in write_eye_detect_single_rank() 628 eye->mid = (eye->min + eye->max) / 2; in write_eye_detect_single_rank() 669 if (eye->max == 0) { in write_eye_detect_single_rank()
|
/SCP-firmware-master/module/clock/include/ |
A D | mod_clock.h | 215 uint64_t max; member
|
/SCP-firmware-master/product/rcar/module/rcar_sd_clock/src/ |
A D | mod_rcar_sd_clock.c | 203 range->max = ctx->rate_table[1]; in sd_clock_get_range() 208 range->max = ctx->rate_table[ctx->config->rate_count - 1]; in sd_clock_get_range()
|
/SCP-firmware-master/module/mock_clock/src/ |
A D | mod_mock_clock.c | 169 range->max = ctx->config->rate_table[ctx->config->rate_count - 1].rate; in mod_mock_clock_get_range()
|
/SCP-firmware-master/module/system_pll/src/ |
A D | mod_system_pll.c | 210 range->max = ctx->config->max_rate; in system_pll_get_range()
|
/SCP-firmware-master/product/morello/module/morello_pll/src/ |
A D | mod_morello_pll.c | 255 range->max = MOD_MORELLO_PLL_RATE_MAX; in morello_pll_get_range()
|
/SCP-firmware-master/product/n1sdp/module/n1sdp_pll/src/ |
A D | mod_n1sdp_pll.c | 235 range->max = MOD_N1SDP_PLL_RATE_MAX; in n1sdp_pll_get_range()
|
/SCP-firmware-master/product/juno/module/juno_hdlcd/src/ |
A D | mod_juno_hdlcd.c | 323 range->max = ctx->config->max_rate; in juno_hdlcd_get_range()
|
/SCP-firmware-master/module/css_clock/src/ |
A D | mod_css_clock.c | 240 range->max = ctx->config->rate_table[ctx->config->rate_count - 1].rate; in css_clock_get_range()
|
/SCP-firmware-master/product/juno/module/juno_cdcel937/src/ |
A D | mod_juno_cdcel937.c | 819 range->max = ctx->config->lookup_table[last_idx].rate_hz; in juno_cdcel937_get_range() 823 range->max = ctx->config->max_rate; in juno_cdcel937_get_range()
|
/SCP-firmware-master/product/juno/module/juno_soc_clock_ram/src/ |
A D | mod_juno_soc_clock_ram.c | 479 range->max = ctx->config->rate_table[ctx->config->rate_count - 1].rate; in juno_soc_clock_get_range()
|
/SCP-firmware-master/product/synquacer/module/synquacer_pik_clock/src/ |
A D | mod_synquacer_pik_clock.c | 489 range->max = ctx->config->rate_table[ctx->config->rate_count - 1].rate; in pik_clock_get_range()
|
/SCP-firmware-master/module/pik_clock/src/ |
A D | mod_pik_clock.c | 477 range->max = ctx->config->rate_table[ctx->config->rate_count - 1].rate; in pik_clock_get_range()
|
/SCP-firmware-master/module/scmi_clock/src/ |
A D | mod_scmi_clock.c | 1358 clock_range[1].low = (uint32_t)info.range.max; in scmi_clock_describe_rates_handler() 1359 clock_range[1].high = (uint32_t)(info.range.max >> 32); in scmi_clock_describe_rates_handler()
|