Home
last modified time | relevance | path

Searched refs:mmio_write_32 (Results 1 – 14 of 14) sorted by relevance

/SCP-firmware-master/product/rcar/module/rcar_system/src/
A Drcar_pwc.c91 mmio_write_32( in rcar_pwrc_set_self_refresh()
97 mmio_write_32(DBSC4_REG_DBACEN, 0); in rcar_pwrc_set_self_refresh()
102 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1); in rcar_pwrc_set_self_refresh()
107 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0); in rcar_pwrc_set_self_refresh()
109 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1); in rcar_pwrc_set_self_refresh()
120 mmio_write_32(DBSC4_REG_DBCALCNF, 0); in rcar_pwrc_set_self_refresh()
124 mmio_write_32(DBSC4_REG_DBCMD, reg); in rcar_pwrc_set_self_refresh()
131 mmio_write_32(DBSC4_REG_DBCMD, reg); in rcar_pwrc_set_self_refresh()
138 mmio_write_32(DBSC4_REG_DBCMD, reg); in rcar_pwrc_set_self_refresh()
145 mmio_write_32(DBSC4_REG_DBCMD, reg); in rcar_pwrc_set_self_refresh()
[all …]
A Drcar_common.c18 mmio_write_32((uintptr_t)RCAR_CPGWPR, ~value); in cpg_write()
19 mmio_write_32(regadr, value); in cpg_write()
A DFreeRTOS_tick_config.c147 mmio_write_32(RCAR_GICC_BASE + GICC_EOIR, c_interrupt); in vApplicationIRQHandler()
/SCP-firmware-master/product/rcar/module/rcar_pd_core/src/
A Drcar_pd_core.c35 mmio_write_32(RCAR_CPGWPR, ~((uint32_t)CPU_PWR_OFF)); in rcar_pwrc_cpuoff()
36 mmio_write_32(off_reg + (cpu_no * 0x0010U), (uint32_t)CPU_PWR_OFF); in rcar_pwrc_cpuoff()
66 mmio_write_32(RCAR_CPGWPR, ~wup_data); in rcar_pwrc_cpuon()
67 mmio_write_32(on_reg, wup_data); in rcar_pwrc_cpuon()
69 mmio_write_32(res_reg, (res_data & (~((uint32_t)1U << (3U - cpu_no))))); in rcar_pwrc_cpuon()
102 mmio_write_32(reg_CPUCMCR, (uint32_t)0x00000000U); in SCU_power_up()
105 mmio_write_32(reg_SYSCIER, (mmio_read_32(reg_SYSCIER) | reg_SYSC_bit)); in SCU_power_up()
106 mmio_write_32(reg_SYSCIMR, (mmio_read_32(reg_SYSCIMR) | reg_SYSC_bit)); in SCU_power_up()
113 mmio_write_32(reg_PWRONCR, 0x0001U); in SCU_power_up()
121 mmio_write_32(reg_SYSCISCR, reg_SYSC_bit); in SCU_power_up()
A Dmod_rcar_pd_core.c138 mmio_write_32(RCAR_CPGWPR, ~CPU_PWR_OFF); in rcar_core_pd_prepare_for_system_suspend()
139 mmio_write_32(RCAR_CA57CPU0CR, CPU_PWR_OFF); in rcar_core_pd_prepare_for_system_suspend()
141 mmio_write_32(RCAR_CA57CPUCMCR, MODE_L2_DOWN); in rcar_core_pd_prepare_for_system_suspend()
/SCP-firmware-master/product/rcar/module/rcar_mstp_clock/src/
A Dmod_rcar_mstp_clock.c97 mmio_write_32(SMSTPCR0, SMSTPCR0_VALUE); in mstp_clock_resume()
98 mmio_write_32(SMSTPCR1, SMSTPCR1_VALUE); in mstp_clock_resume()
99 mmio_write_32(SMSTPCR2, SMSTPCR2_VALUE); in mstp_clock_resume()
100 mmio_write_32(SMSTPCR3, SMSTPCR3_VALUE); in mstp_clock_resume()
101 mmio_write_32(SMSTPCR4, SMSTPCR4_VALUE); in mstp_clock_resume()
102 mmio_write_32(SMSTPCR5, SMSTPCR5_VALUE); in mstp_clock_resume()
103 mmio_write_32(SMSTPCR6, SMSTPCR6_VALUE); in mstp_clock_resume()
104 mmio_write_32(SMSTPCR7, SMSTPCR7_VALUE); in mstp_clock_resume()
105 mmio_write_32(SMSTPCR8, SMSTPCR8_VALUE); in mstp_clock_resume()
106 mmio_write_32(SMSTPCR9, SMSTPCR9_VALUE); in mstp_clock_resume()
[all …]
/SCP-firmware-master/product/rcar/module/rcar_pd_sysc/src/
A Drcar_pd_sysc.c47 mmio_write_32( in rcar_sysc_pwr_on_off()
64 mmio_write_32((SYSC_BASE_ADDR + SYSCIMR), (syscimr | isr_mask)); in rcar_sysc_power()
65 mmio_write_32((SYSC_BASE_ADDR + SYSCIER), (syscier | isr_mask)); in rcar_sysc_power()
66 mmio_write_32((SYSC_BASE_ADDR + SYSCISCR), isr_mask); in rcar_sysc_power()
97 mmio_write_32((SYSC_BASE_ADDR + SYSCISCR), isr_mask); in rcar_sysc_power()
/SCP-firmware-master/arch/arm/armv8-a/include/lib/
A Dmmio.h41 static inline void mmio_write_32(uintptr_t addr, uint32_t value) in mmio_write_32() function
63 mmio_write_32(addr, mmio_read_32(addr) & ~clear); in mmio_clrbits_32()
68 mmio_write_32(addr, mmio_read_32(addr) | set); in mmio_setbits_32()
76 mmio_write_32(addr, (mmio_read_32(addr) & ~clear) | set); in mmio_clrsetbits_32()
/SCP-firmware-master/product/rcar/module/rcar_reset/src/
A Dmod_rcar_reset.c43 mmio_write_32((CPG_BASE + srcr[ctx->config->control_reg]), in rcar_auto_domain()
50 mmio_write_32((CPG_BASE + SRSTCLR(ctx->config->control_reg)), in rcar_auto_domain()
62 mmio_write_32((CPG_BASE + srcr[ctx->config->control_reg]), in rcar_assert_domain()
74 mmio_write_32((CPG_BASE + SRSTCLR(ctx->config->control_reg)), in rcar_deassert_domain()
/SCP-firmware-master/product/rcar/module/rcar_scif/src/
A Dmod_rcar_scif.c84 mmio_write_32(CPG_CPGWPR, ~status); in mod_rcar_scif_set_baud_rate()
85 mmio_write_32(CPG_SMSTPCR2, status); in mod_rcar_scif_set_baud_rate()
93 mmio_write_32(CPG_CPGWPR, ~status); in mod_rcar_scif_set_baud_rate()
94 mmio_write_32(CPG_SMSTPCR3, status); in mod_rcar_scif_set_baud_rate()
/SCP-firmware-master/arch/arm/armv8-a/src/
A Darch_gic.c207 mmio_write_32(base + GICD_ISENABLER + (n << 2), val); in gicd_write_isenabler()
221 mmio_write_32(base + GICD_ICENABLER + (n << 2), val); in gicd_write_icenabler()
235 mmio_write_32(base + GICD_ISPENDR + (n << 2), val); in gicd_write_ispendr()
249 mmio_write_32(base + GICD_ICPENDR + (n << 2), val); in gicd_write_icpendr()
299 mmio_write_32(base + GICC_CTLR, val); in gicc_write_ctlr()
304 mmio_write_32(base + GICC_PMR, val); in gicc_write_pmr()
/SCP-firmware-master/product/rcar/module/rcar_clock/src/
A Dmod_rcar_clock.c575 mmio_write_32(CPG_PLL0CR, val); in pll0_clk_set_rate()
632 mmio_write_32(CPG_PLL2CR, val); in pll2_clk_set_rate()
707 mmio_write_32(CPG_FRQCRC, val); in z_clk_set_rate()
715 mmio_write_32(CPG_FRQCRB, kick); in z_clk_set_rate()
803 mmio_write_32(CPG_FRQCRC, val); in z2_clk_set_rate()
811 mmio_write_32(CPG_FRQCRB, kick); in z2_clk_set_rate()
/SCP-firmware-master/product/rcar/module/rcar_sd_clock/src/
A Dmod_rcar_sd_clock.c84 mmio_write_32(ctx->config->control_reg, value); in do_sd_clock_set_rate()
89 mmio_write_32(ctx->config->control_reg, value); in do_sd_clock_set_rate()
174 mmio_write_32(ctx->config->control_reg, value); in sd_clock_set_state()
/SCP-firmware-master/product/rcar/module/rcar_reg_sensor/src/
A Dmod_rcar_reg_sensor.c49 mmio_write_32(tsc->base + reg, data); in rcar_gen3_thermal_write()

Completed in 16 milliseconds