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Searched refs:parent_clk (Results 1 – 2 of 2) sorted by relevance

/SCP-firmware-master/product/rcar/module/rcar_sd_clock/src/
A Dmod_rcar_sd_clock.c257 ctx->current_rate = module_ctx.parent_clk[ctx->config->parent] / div_value; in sd_clock_hw_initial_set_state()
260 rate = module_ctx.parent_clk[ctx->config->parent] / ctx->config->div; in sd_clock_hw_initial_set_state()
339 module_ctx.parent_clk[CLK_EXTAL] = ext->ext_clk_rate; in sd_clock_init()
342 module_ctx.parent_clk[CLK_PLL1_DIV2] = module_ctx.parent_clk[CLK_PLL1] / 2; in sd_clock_init()
343 module_ctx.parent_clk[CLK_PLL1_DIV4] = module_ctx.parent_clk[CLK_PLL1] / 4; in sd_clock_init()
345 module_ctx.parent_clk[CLK_S0] = module_ctx.parent_clk[CLK_PLL1_DIV2] / 2; in sd_clock_init()
346 module_ctx.parent_clk[CLK_S1] = module_ctx.parent_clk[CLK_PLL1_DIV2] / 3; in sd_clock_init()
347 module_ctx.parent_clk[CLK_S2] = module_ctx.parent_clk[CLK_PLL1_DIV2] / 4; in sd_clock_init()
348 module_ctx.parent_clk[CLK_S3] = module_ctx.parent_clk[CLK_PLL1_DIV2] / 6; in sd_clock_init()
349 module_ctx.parent_clk[CLK_SDSRC] = module_ctx.parent_clk[CLK_PLL1_DIV2] / 2; in sd_clock_init()
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/SCP-firmware-master/product/rcar/module/rcar_sd_clock/include/
A Dmod_rcar_sd_clock.h99 uint32_t parent_clk[CLOCK_PARENT_IDX_COUNT]; member

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