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Searched refs:reg (Results 1 – 25 of 67) sorted by relevance

123

/SCP-firmware-master/module/cdns_i2c/src/
A Dmod_cdns_i2c.c38 ((reg) = (((reg) & ~(mask)) | (((val) << (shift)) & (mask))))
41 #define I2C_REG_W(reg, mask, shift, val) ((reg) = ((val) << (shift)) & (mask)) argument
44 #define I2C_REG_R(reg, mask, shift) (((reg) & (mask)) >> (shift)) argument
57 struct cdns_i2c_reg *reg; member
118 uint16_t reg; in clear_isr() local
120 reg = I2C_REG_R(device_ctx->reg->ISR, I2C_ISR_MASK, I2C_ISR_SHIFT); in clear_isr()
121 I2C_REG_W(device_ctx->reg->ISR, I2C_ISR_MASK, I2C_ISR_SHIFT, reg); in clear_isr()
133 isr = ctx->reg->ISR; in i2c_isr()
134 ctx->reg->ISR = isr; in i2c_isr()
211 ctx->reg->CR, in i2c_isr()
[all …]
/SCP-firmware-master/product/rcar/module/rcar_scif/src/
A Dmod_rcar_scif.c77 assert(reg); in mod_rcar_scif_set_baud_rate()
107 reg->SCFSR = SCFSR_INIT_DATA; in mod_rcar_scif_set_baud_rate()
108 reg->SCLSR = 0; in mod_rcar_scif_set_baud_rate()
110 reg->SCSCR = (reg->SCSCR & ~SCSCR_CKE_MASK) | SCSCR_CKE_INT_CLK; in mod_rcar_scif_set_baud_rate()
112 reg->SCSMR = SCSMR_INIT_DATA; in mod_rcar_scif_set_baud_rate()
123 reg->DL = DL_INIT_DATA; in mod_rcar_scif_set_baud_rate()
124 reg->CKS = CKS_INIT_DATA; in mod_rcar_scif_set_baud_rate()
128 reg->SCFCR = SCFCR_INIT_DATA; in mod_rcar_scif_set_baud_rate()
129 reg->SCSCR = (reg->SCSCR | (SCSCR_TE_EN | SCSCR_RE_EN)); in mod_rcar_scif_set_baud_rate()
147 reg->SCFTDR = c; in mod_rcar_scif_putch()
[all …]
/SCP-firmware-master/module/pcie_integ_ctrl/src/
A Dmod_pcie_integ_ctrl.c50 struct pcie_ctrl_reg_set *reg, in pcie_integ_ctrl_configure_registers() argument
53 reg->ECAM1_START_ADDR = PCIE_INTEG_CTRL_REG_START_ADDR_EN( in pcie_integ_ctrl_configure_registers()
72 struct pcie_ctrl_reg_set *reg; in configure_pcie_ecam_mmio_space() local
81 reg = &pcie_integ_ctrl_reg->pcie_ctrl_x4_0; in configure_pcie_ecam_mmio_space()
86 pcie_integ_ctrl_configure_registers(reg, cfg); in configure_pcie_ecam_mmio_space()
89 reg = &pcie_integ_ctrl_reg->pcie_ctrl_x4_1; in configure_pcie_ecam_mmio_space()
94 pcie_integ_ctrl_configure_registers(reg, cfg); in configure_pcie_ecam_mmio_space()
97 reg = &pcie_integ_ctrl_reg->pcie_ctrl_x8; in configure_pcie_ecam_mmio_space()
102 pcie_integ_ctrl_configure_registers(reg, cfg); in configure_pcie_ecam_mmio_space()
105 reg = &pcie_integ_ctrl_reg->pcie_ctrl_x16; in configure_pcie_ecam_mmio_space()
[all …]
/SCP-firmware-master/product/synquacer/module/hsspi/src/
A Dmod_hsspi.c25 struct hsspi_reg *reg; member
70 reg->MCTRL |= MCTRL_MEN(ENABLE); in enable_module()
80 struct hsspi_reg *reg, in set_pcc() argument
98 struct hsspi_reg *reg, in set_clock_source() argument
110 struct hsspi_reg *reg, in set_cscfg() argument
144 struct hsspi_reg *reg, in enable_cs_access_mode() argument
203 struct hsspi_reg *reg, in get_dummy_command_len() argument
232 struct hsspi_reg *reg, in get_command_len() argument
245 struct hsspi_reg *reg, in set_command_sequence() argument
552 enable_module(ctx->reg, false); in csmode_init()
[all …]
/SCP-firmware-master/product/synquacer/module/f_uart3/src/
A Dmod_f_uart3.c98 struct f_uart3_reg *reg; in mod_f_uart3_enable() local
103 reg = (struct f_uart3_reg *)cfg->reg_base; in mod_f_uart3_enable()
107 reg->LCR |= F_UART3_LCR_DLAB; in mod_f_uart3_enable()
117 reg->LCR &= ~F_UART3_LCR_DLAB; in mod_f_uart3_enable()
121 reg->LCR = F_UART3_LCR_WLS_8; in mod_f_uart3_enable()
123 reg->LCR |= F_UART3_LCR_PEN; in mod_f_uart3_enable()
125 reg->LCR |= F_UART3_LCR_EPS; in mod_f_uart3_enable()
131 reg->IER = 0x0; in mod_f_uart3_enable()
147 while ((reg->LSR & F_UART3_LSR_THRE) == 0x0) in mod_f_uart3_putch()
150 reg->RFR_TFR = ch; in mod_f_uart3_putch()
[all …]
/SCP-firmware-master/product/n1sdp/module/n1sdp_timer_sync/src/
A Dmod_n1sdp_timer_sync.c49 struct timer_sync_reg *reg; member
83 while (dev_ctx->reg->SLVCHIP_GCNT_INT_STATUS & in timer_sync_isr()
85 dev_ctx->reg->SLVCHIP_GCNT_INT_CLR = SLVCHIP_GCNT_INT_CLR_MASK; in timer_sync_isr()
91 dev_ctx->reg->SLVCHIP_GCNT_SYNC_CTRL = 0; in timer_sync_isr()
92 dev_ctx->reg->SLVCHIP_GCNT_SYNC_CTRL = SLV_GCNT_SYNC_CTRL_EN_MASK; in timer_sync_isr()
130 device_ctx->reg->GCNT_TIMEOUT = device_ctx->config->sync_timeout; in n1sdp_sync_primary_timer()
132 device_ctx->reg->MST_GCNT_SYNC_CTRL = MST_GCNT_SYNC_CTRL_EN_MASK; in n1sdp_sync_primary_timer()
170 device_ctx->reg->SLVCHIP_GCNT_SYNC_INTERVAL = in n1sdp_sync_secondary_timer()
172 device_ctx->reg->SLVCHIP_GCNT_OFF_THRESHOLD = in n1sdp_sync_secondary_timer()
208 if (config->reg == 0) { in n1sdp_timer_sync_device_init()
[all …]
/SCP-firmware-master/product/rcar/module/rcar_system/src/
A Drcar_pwc.c80 uint32_t reg = mmio_read_32(RCAR_PRR); in rcar_pwrc_set_self_refresh() local
83 product = reg & RCAR_PRODUCT_MASK; in rcar_pwrc_set_self_refresh()
84 cut = reg & RCAR_CUT_MASK; in rcar_pwrc_set_self_refresh()
122 reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL | in rcar_pwrc_set_self_refresh()
124 mmio_write_32(DBSC4_REG_DBCMD, reg); in rcar_pwrc_set_self_refresh()
129 reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL | in rcar_pwrc_set_self_refresh()
131 mmio_write_32(DBSC4_REG_DBCMD, reg); in rcar_pwrc_set_self_refresh()
136 reg = DBSC4_SET_DBCMD_OPC_MRW | DBSC4_SET_DBCMD_CH_ALL | in rcar_pwrc_set_self_refresh()
138 mmio_write_32(DBSC4_REG_DBCMD, reg); in rcar_pwrc_set_self_refresh()
143 reg = DBSC4_SET_DBCMD_OPC_PD | DBSC4_SET_DBCMD_CH_ALL | in rcar_pwrc_set_self_refresh()
[all …]
A Drcar_common.c25 uint32_t reg; in mstpcr_write() local
26 reg = mmio_read_32(mstpcr); in mstpcr_write()
27 reg &= ~target_bit; in mstpcr_write()
28 cpg_write(mstpcr, reg); in mstpcr_write()
A Drcar_iic_dvfs.c95 uint8_t reg, stop; in IIC_DVFS_FUNC() local
101 reg = mmio_read_8(IIC_DVFS_REG_ICSR); in IIC_DVFS_FUNC()
110 mmio_write_8(IIC_DVFS_REG_ICSR, reg); in IIC_DVFS_FUNC()
117 } while (reg == 0); in IIC_DVFS_FUNC()
122 mmio_write_8(IIC_DVFS_REG_ICSR, reg); in IIC_DVFS_FUNC()
127 if (reg == 0) in IIC_DVFS_FUNC()
149 reg = mmio_read_8(IIC_DVFS_REG_ICIC); in IIC_DVFS_FUNC()
151 mmio_write_8(IIC_DVFS_REG_ICIC, reg); in IIC_DVFS_FUNC()
154 mmio_write_8(IIC_DVFS_REG_ICSR, reg); in IIC_DVFS_FUNC()
178 uint32_t reg, lsi_product; in IIC_DVFS_FUNC() local
[all …]
A DFreeRTOS_tick_config.c25 uint32_t reg; in init_generic_timer() local
42 reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); in init_generic_timer()
50 if (RCAR_PRODUCT_H3_CUT10 == reg) { in init_generic_timer()
/SCP-firmware-master/product/rcar/module/rcar_reg_sensor/src/
A Dmod_rcar_reg_sensor.c39 uint32_t reg) in rcar_gen3_thermal_read() argument
41 return mmio_read_32(tsc->base + reg); in rcar_gen3_thermal_read()
46 uint32_t reg, in rcar_gen3_thermal_write() argument
49 mmio_write_32(tsc->base + reg, data); in rcar_gen3_thermal_write()
89 int reg; in rcar_gen3_thermal_get_temp() local
92 reg = rcar_gen3_thermal_read(tsc, REG_GEN3_TEMP) & CTEMP_MASK; in rcar_gen3_thermal_get_temp()
94 if (reg <= thcode[tsc->id][1]) in rcar_gen3_thermal_get_temp()
95 val = FIXPT_DIV(FIXPT_INT(reg) - tsc->coef.b1, tsc->coef.a1); in rcar_gen3_thermal_get_temp()
193 pid = ADR2INDEX(config->reg); in reg_sensor_start()
196 tsc->base = config->reg; in reg_sensor_start()
[all …]
/SCP-firmware-master/product/juno/module/juno_cdcel937/src/
A Djuno_cdcel937.h69 static inline uint8_t read_field(uint8_t *reg, struct field f) in read_field() argument
71 return (reg[f.reg_idx] & f.mask) >> f.pos; in read_field()
75 static inline void write_field(uint8_t *reg, struct field f, uint8_t value) in write_field() argument
77 reg[f.reg_idx] &= ~f.mask; in write_field()
78 reg[f.reg_idx] |= ((value << f.pos) & f.mask); in write_field()
91 uint8_t reg[CFG_REG0_COUNT]; member
110 uint8_t reg[CFG_REG6_COUNT]; member
133 uint8_t reg[CFG_REG_Y1_COUNT]; member
197 uint8_t reg[PLL_CFG_REG_COUNT]; member
A Dmod_juno_cdcel937.c114 config6.reg[0] = 0; in set_block_access_length()
116 write_field(config6.reg, CFG_REG6_EEWRITE, 0); in set_block_access_length()
122 i2c_transmit[1] = config6.reg[0]; in set_block_access_length()
155 fwk_str_memcpy(&i2c_transmit[2], &(config->reg[1]), 8); in write_configuration()
188 config->reg, in read_configuration()
214 config->reg, in read_configuration_y1()
425 write_field(pll_config.reg, PLL_CFG_REG_P, (uint8_t)P); in set_rate_write_pll_config()
437 write_field(pll_config.reg, PLL_CFG_REG_VCO_RANGE, in set_rate_write_pll_config()
440 write_field(pll_config.reg, PLL_CFG_REG_VCO_RANGE, in set_rate_write_pll_config()
443 write_field(pll_config.reg, PLL_CFG_REG_VCO_RANGE, in set_rate_write_pll_config()
[all …]
/SCP-firmware-master/arch/arm/armv8-a/include/
A Dasm_macros.S37 .macro dcache_line_size reg, tmp
40 mov \reg, #4
41 lsl \reg, \reg, \tmp
45 .macro icache_line_size reg, tmp
48 mov \reg, #4
49 lsl \reg, \reg, \tmp
/SCP-firmware-master/product/morello/module/morello_mhu/src/
A Dmod_mhu.c71 struct mhu_reg *reg; in mhu_isr() local
88 reg = (struct mhu_reg *)device_ctx->config->in; in mhu_isr()
91 while (reg->STAT != 0) { in mhu_isr()
92 slot = __builtin_ctz(reg->STAT); in mhu_isr()
104 reg->CLEAR = 1 << slot; in mhu_isr()
116 struct mhu_reg *reg; in raise_interrupt() local
120 reg = (struct mhu_reg *)device_ctx->config->out; in raise_interrupt()
122 reg->SET |= (1 << slot); in raise_interrupt()
/SCP-firmware-master/product/n1sdp/module/n1sdp_mhu/src/
A Dmod_mhu.c71 struct mhu_reg *reg; in mhu_isr() local
88 reg = (struct mhu_reg *)device_ctx->config->in; in mhu_isr()
91 while (reg->STAT != 0) { in mhu_isr()
92 slot = __builtin_ctz(reg->STAT); in mhu_isr()
104 reg->CLEAR = 1 << slot; in mhu_isr()
116 struct mhu_reg *reg; in raise_interrupt() local
120 reg = (struct mhu_reg *)device_ctx->config->out; in raise_interrupt()
122 reg->SET |= (1 << slot); in raise_interrupt()
/SCP-firmware-master/module/mhu/src/
A Dmod_mhu.c72 struct mhu_reg *reg; in mhu_isr() local
92 reg = (struct mhu_reg *)device_ctx->config->in; in mhu_isr()
95 while (reg->STAT != 0) { in mhu_isr()
96 slot = (unsigned int)__builtin_ctz(reg->STAT); in mhu_isr()
112 reg->CLEAR = 1U << slot; in mhu_isr()
124 struct mhu_reg *reg; in raise_interrupt() local
129 reg = (struct mhu_reg *)device_ctx->config->out; in raise_interrupt()
131 reg->SET |= (1U << slot); in raise_interrupt()
/SCP-firmware-master/module/reg_sensor/
A DModule.cmake8 set(SCP_MODULE "reg-sensor")
9 set(SCP_MODULE_TARGET "module-reg-sensor")
/SCP-firmware-master/product/rcar/module/rcar_reg_sensor/
A DModule.cmake8 set(SCP_MODULE "rcar-reg-sensor")
10 set(SCP_MODULE_TARGET "module-rcar-reg-sensor")
/SCP-firmware-master/module/pl011/src/
A Dmod_pl011.c101 struct pl011_reg *reg = (void *)cfg->reg_base; in mod_pl011_set_baud_rate() local
109 fwk_assert(reg != NULL); in mod_pl011_set_baud_rate()
139 reg->IBRD = (uint16_t)divisor_integer; in mod_pl011_set_baud_rate()
140 reg->FBRD = divisor_fractional; in mod_pl011_set_baud_rate()
149 struct pl011_reg *reg = (void *)cfg->reg_base; in mod_pl011_enable() local
156 reg->ECR = PL011_ECR_CLR; in mod_pl011_enable()
172 while (reg->FR & PL011_FR_TXFF) { in mod_pl011_putch()
176 reg->DR = (uint16_t)ch; in mod_pl011_putch()
190 if (reg->FR & PL011_FR_RXFE) { in mod_pl011_getch()
194 *ch = (char)reg->DR; in mod_pl011_getch()
[all …]
/SCP-firmware-master/product/rcar/scp_ramfw/
A Dconfig_sensor.c35 .reg = (uintptr_t)(SENSOR_SOC_TEMP1),
42 .reg = (uintptr_t)(SENSOR_SOC_TEMP2),
49 .reg = (uintptr_t)(SENSOR_SOC_TEMP3),
/SCP-firmware-master/product/juno/module/juno_ppu/src/
A Dmod_juno_ppu.c46 struct ppu_reg *reg; member
167 struct ppu_reg *reg; in ppu_request_state() local
169 reg = ppu_ctx->reg; in ppu_request_state()
170 fwk_assert(reg != NULL); in ppu_request_state()
174 reg->POWER_POLICY = (uint32_t)mode; in ppu_request_state()
183 struct ppu_reg *reg; in ppu_set_state_and_wait() local
187 reg = ppu_ctx->reg; in ppu_set_state_and_wait()
188 fwk_assert(reg != NULL); in ppu_set_state_and_wait()
194 reg->POWER_POLICY = (uint32_t)mode; in ppu_set_state_and_wait()
197 params.reg = reg; in ppu_set_state_and_wait()
[all …]
/SCP-firmware-master/module/ppu_v0/src/
A Dppu_v0.c17 struct ppu_v0_reg *reg; member
28 (params->reg->POWER_STATUS & in ppu_v0_set_power_status_check()
77 params.reg = ppu; in ppu_v0_set_power_mode()
/SCP-firmware-master/module/reg_sensor/include/
A Dmod_reg_sensor.h30 uintptr_t reg; member
/SCP-firmware-master/product/optee-fvp/fw/
A Dconfig_sensor.c31 .reg = (uintptr_t)(soc_temp),
38 .reg = (uintptr_t)(ddr_temp),

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