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Searched refs:ARM_DRAM1_BASE (Results 1 – 15 of 15) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/arm/board/morello/
A Dmorello_bl2_setup.c74 zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE); in dmc_ecc_setup()
75 flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE); in dmc_ecc_setup()
116 if (tag_mem_base < ARM_DRAM1_BASE) { in dmc_ecc_setup()
117 tag_mem_base += ARM_DRAM1_BASE; in dmc_ecc_setup()
119 tag_mem_base = tag_mem_base - ARM_DRAM1_BASE + in dmc_ecc_setup()
/arm-trusted-firmware-2.8.0/plat/arm/board/corstone1000/common/include/
A Dplatform_def.h99 #define ARM_DRAM1_BASE UL(0x80000000) macro
101 #define ARM_DRAM1_END (ARM_DRAM1_BASE + ARM_DRAM1_SIZE - 1)
104 #define ARM_DRAM2_BASE ARM_DRAM1_BASE
108 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
168 #define BL33_BASE ARM_DRAM1_BASE
170 #define BL33_LIMIT (ARM_DRAM1_BASE + PLAT_ARM_MAX_BL33_SIZE)
/arm-trusted-firmware-2.8.0/plat/arm/board/a5ds/include/
A Dplatform_def.h20 #define ARM_DRAM1_BASE UL(0x80000000) macro
22 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \
97 #define BOOT_BASE ARM_DRAM1_BASE
100 #define ARM_NS_DRAM1_BASE (ARM_DRAM1_BASE + BOOT_SIZE)
271 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + U(0x8000000))
/arm-trusted-firmware-2.8.0/plat/arm/board/n1sdp/
A Dn1sdp_bl2_setup.c39 zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE); in dmc_ecc_setup()
40 flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE); in dmc_ecc_setup()
/arm-trusted-firmware-2.8.0/plat/arm/board/fvp_ve/include/
A Dplatform_def.h24 #define ARM_DRAM1_BASE UL(0x80000000) macro
26 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \
34 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
258 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + U(0x8000000))
/arm-trusted-firmware-2.8.0/include/plat/arm/common/
A Darm_def.h128 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
136 #define ARM_L1_GPT_ADDR_BASE (ARM_DRAM1_BASE + \
147 #define ARM_EL3_RMM_SHARED_BASE (ARM_DRAM1_BASE + \
163 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
216 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
223 #define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE macro
225 #define ARM_DRAM1_BASE ULL(0x80000000) macro
229 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \
/arm-trusted-firmware-2.8.0/plat/arm/board/corstone700/common/include/
A Dplatform_def.h51 #define ARM_DRAM1_BASE UL(0x80000000) macro
53 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \
55 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
/arm-trusted-firmware-2.8.0/plat/arm/board/n1sdp/include/
A Dplatform_def.h55 #define N1SDP_REMOTE_DRAM1_BASE ARM_DRAM1_BASE + \
217 ARM_DRAM1_BASE, \
/arm-trusted-firmware-2.8.0/plat/arm/board/juno/
A Djuno_tzmp1_def.h43 #define JUNO_NS_DRAM1_PT1_BASE ARM_DRAM1_BASE
/arm-trusted-firmware-2.8.0/plat/arm/common/aarch32/
A Darm_bl2_mem_params_desc.c83 .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE
/arm-trusted-firmware-2.8.0/plat/arm/board/morello/include/
A Dplatform_def.h182 ARM_DRAM1_BASE, \
/arm-trusted-firmware-2.8.0/plat/arm/board/tc/include/
A Dplatform_def.h38 #define TC_NS_DRAM1_BASE ARM_DRAM1_BASE
/arm-trusted-firmware-2.8.0/plat/arm/css/sgi/include/
A Dsgi_base_platform_def.h276 {CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE, \
/arm-trusted-firmware-2.8.0/plat/arm/board/fvp/include/
A Dplatform_def.h121 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000))
/arm-trusted-firmware-2.8.0/plat/arm/common/aarch64/
A Darm_bl2_mem_params_desc.c208 .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE

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