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Searched refs:ARM_DRAM2_BASE (Results 1 – 11 of 11) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/arm/board/fvp/
A Dfvp_drtm_addr.c28 } else if ((region_start >= ARM_DRAM2_BASE) && in plat_drtm_validate_ns_region()
29 (region_start < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE)) && in plat_drtm_validate_ns_region()
30 (region_end >= ARM_DRAM2_BASE) && in plat_drtm_validate_ns_region()
31 (region_end < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { in plat_drtm_validate_ns_region()
/arm-trusted-firmware-2.8.0/plat/arm/board/morello/
A Dmorello_bl2_setup.c78 ARM_DRAM2_BASE, ARM_DRAM2_BASE + dram2_size); in dmc_ecc_setup()
79 zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size); in dmc_ecc_setup()
80 flush_dcache_range(ARM_DRAM2_BASE, dram2_size); in dmc_ecc_setup()
120 ARM_DRAM2_BASE; in dmc_ecc_setup()
/arm-trusted-firmware-2.8.0/plat/arm/board/n1sdp/
A Dn1sdp_bl2_setup.c41 zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size); in dmc_ecc_setup()
42 flush_dcache_range(ARM_DRAM2_BASE, dram2_size); in dmc_ecc_setup()
/arm-trusted-firmware-2.8.0/plat/arm/common/
A Darm_pm.c119 if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint < in arm_validate_ns_entrypoint()
120 (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { in arm_validate_ns_entrypoint()
A Darm_nor_psci_mem_protect.c29 {ARM_DRAM2_BASE, 1u << ONE_GB_SHIFT},
/arm-trusted-firmware-2.8.0/plat/arm/board/fvp_ve/include/
A Dplatform_def.h29 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE macro
31 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \
101 ARM_DRAM2_BASE, \
/arm-trusted-firmware-2.8.0/include/plat/arm/common/
A Dplat_arm.h48 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
63 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
72 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
A Darm_def.h232 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE macro
234 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \
286 ARM_DRAM2_BASE, \
/arm-trusted-firmware-2.8.0/plat/arm/board/juno/
A Djuno_security.c52 {ARM_DRAM2_BASE, ARM_DRAM2_END,
/arm-trusted-firmware-2.8.0/plat/arm/css/sgi/include/
A Dsgi_base_platform_def.h279 {CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE, \
/arm-trusted-firmware-2.8.0/plat/arm/board/corstone1000/common/include/
A Dplatform_def.h104 #define ARM_DRAM2_BASE ARM_DRAM1_BASE macro

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