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/arm-trusted-firmware-2.8.0/plat/imx/common/include/
A Dimx_clock.h193 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
204 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOTUSB_PLL ((BIT(26) | BIT(25) | BIT(24))
226 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
259 #define CCM_TRGT_MUX_AHB_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
358 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
369 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
380 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24))
424 #define CCM_TRGT_MUX_EIM_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
490 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_EXT_CLK4 ((BIT(26) | BIT(25) | BIT(24))
853 #define CCM_TRGT_MUX_CCM_CLKO1_REF_1M ((BIT(26) | BIT(25) | BIT(24))
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A Dimx_io_mux.h133 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT3_CSI_PIXCLK (BIT(1) | BIT(0))
135 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT5_GPIO4_IO14 (BIT(2) | BIT(0))
136 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT6_EPDC_VCOM0 (BIT(2) | BIT(1))
142 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT3_CSI_MCLK (BIT(1) | BIT(0))
144 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT5_GPIO4_IO15 (BIT(1) | BIT(0))
145 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT6_EPDC_VCOM1 (BIT(2) | BIT(1))
314 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_3_X6 (BIT(1) | BIT(0))
330 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_3_X6 (BIT(1) | BIT(0))
362 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_3_X6 (BIT(1) | BIT(0))
378 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_3_X6 (BIT(1) | BIT(0))
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A Dimx_csu.h17 #define CSU_CSL_LOCK_S1 BIT(24)
18 #define CSU_CSL_NSW_S1 BIT(23)
19 #define CSU_CSL_NUW_S1 BIT(22)
20 #define CSU_CSL_SSW_S1 BIT(21)
21 #define CSU_CSL_SUW_S1 BIT(20)
22 #define CSU_CSL_NSR_S1 BIT(19)
23 #define CSU_CSL_NUR_S1 BIT(18)
27 #define CSU_CSL_NSW_S2 BIT(7)
28 #define CSU_CSL_NUW_S2 BIT(6)
29 #define CSU_CSL_SSW_S2 BIT(5)
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/arm-trusted-firmware-2.8.0/include/drivers/st/
A Dstm32mp15_rcc.h238 #define RCC_TZCR_TZEN BIT(0)
239 #define RCC_TZCR_MCKPROT BIT(1)
333 #define RCC_PLL1CR_PLLON BIT(0)
336 #define RCC_PLL1CR_DIVPEN BIT(4)
337 #define RCC_PLL1CR_DIVQEN BIT(5)
369 #define RCC_PLL2CR_PLLON BIT(0)
488 #define RCC_BDCR_LSEON BIT(0)
489 #define RCC_BDCR_LSEBYP BIT(1)
490 #define RCC_BDCR_LSERDY BIT(2)
491 #define RCC_BDCR_DIGBYP BIT(3)
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A Dstm32mp13_rcc.h340 #define RCC_BDCR_LSEON BIT(0)
341 #define RCC_BDCR_LSEBYP BIT(1)
342 #define RCC_BDCR_LSERDY BIT(2)
343 #define RCC_BDCR_DIGBYP BIT(3)
346 #define RCC_BDCR_LSECSSON BIT(8)
347 #define RCC_BDCR_LSECSSD BIT(9)
350 #define RCC_BDCR_RTCCKEN BIT(20)
461 #define RCC_PLL1CR_PLLON BIT(0)
497 #define RCC_PLL2CR_PLLON BIT(0)
533 #define RCC_PLL3CR_PLLON BIT(0)
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A Dstm32_uart_regs.h26 #define USART_CR1_UE BIT(0)
27 #define USART_CR1_UESM BIT(1)
28 #define USART_CR1_RE BIT(2)
29 #define USART_CR1_TE BIT(3)
30 #define USART_CR1_IDLEIE BIT(4)
32 #define USART_CR1_TCIE BIT(6)
34 #define USART_CR1_PEIE BIT(8)
35 #define USART_CR1_PS BIT(9)
36 #define USART_CR1_PCE BIT(10)
38 #define USART_CR1_M (BIT(28) | BIT(12))
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A Dstm32_i2c.h15 #define I2C_CR1_PE BIT(0)
16 #define I2C_CR1_TXIE BIT(1)
17 #define I2C_CR1_RXIE BIT(2)
18 #define I2C_CR1_ADDRIE BIT(3)
19 #define I2C_CR1_NACKIE BIT(4)
20 #define I2C_CR1_STOPIE BIT(5)
21 #define I2C_CR1_TCIE BIT(6)
22 #define I2C_CR1_ERRIE BIT(7)
28 #define I2C_CR1_SBC BIT(16)
65 #define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10))
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/arm-trusted-firmware-2.8.0/drivers/imx/uart/
A Dimx_uart.h13 #define IMX_UART_RXD_ERR BIT(14)
16 #define IMX_UART_RXD_BRK BIT(11)
28 #define IMX_UART_CR1_IREN BIT(7)
82 #define IMX_UART_FCR_TXTL_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12) |\
83 BIT(11) | BIT(10))
85 #define IMX_UART_FCR_RFDIV_MASK (BIT(9) | BIT(8) | BIT(7))
86 #define IMX_UART_FCR_RFDIV7 (BIT(9) | BIT(8))
87 #define IMX_UART_FCR_RFDIV1 (BIT(9) | BIT(7))
89 #define IMX_UART_FCR_RFDIV3 (BIT(8) | BIT(7))
94 #define IMX_UART_FCR_RXTL_MASK (BIT(5) | BIT(4) | BIT(3) | BIT(2) |\
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/arm-trusted-firmware-2.8.0/drivers/renesas/rcar/pfc/V3M/
A Dpfc_init_v3m.c20 #define GPSR0_DU_DB7 BIT(17)
21 #define GPSR0_DU_DB6 BIT(16)
22 #define GPSR0_DU_DB5 BIT(15)
23 #define GPSR0_DU_DB4 BIT(14)
24 #define GPSR0_DU_DB3 BIT(13)
28 #define GPSR0_DU_DG5 BIT(9)
29 #define GPSR0_DU_DG4 BIT(8)
30 #define GPSR0_DU_DG3 BIT(7)
31 #define GPSR0_DU_DG2 BIT(6)
32 #define GPSR0_DU_DR7 BIT(5)
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/arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mp/include/
A Dgpc_reg.h42 #define IRQ_SRC_C1 BIT(29)
43 #define IRQ_SRC_C0 BIT(28)
44 #define IRQ_SRC_C3 BIT(23)
45 #define IRQ_SRC_C2 BIT(22)
52 #define L2PGE BIT(31)
54 #define EN_PLAT_PDN BIT(4)
60 #define SLPCR_VSTBY BIT(2)
110 #define AUDIOMIX_ADB400_SYNC (BIT(4) | BIT(15))
111 #define MLMIX_ADB400_SYNC (BIT(7) | BIT(8))
119 #define AUDIOMIX_ADB400_ACK (BIT(20) | BIT(31))
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/arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mm/include/
A Dgpc_reg.h40 #define IRQ_SRC_C1 BIT(29)
41 #define IRQ_SRC_C0 BIT(28)
42 #define IRQ_SRC_C3 BIT(23)
43 #define IRQ_SRC_C2 BIT(22)
50 #define L2PGE BIT(31)
51 #define EN_L2_WFI_PDN BIT(5)
52 #define EN_PLAT_PDN BIT(4)
58 #define SLPCR_VSTBY BIT(2)
59 #define SLPCR_SBYOS BIT(1)
76 #define SLT_PLAT_PDN BIT(8)
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/arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mn/include/
A Dgpc_reg.h40 #define IRQ_SRC_C1 BIT(29)
41 #define IRQ_SRC_C0 BIT(28)
42 #define IRQ_SRC_C3 BIT(23)
43 #define IRQ_SRC_C2 BIT(22)
50 #define L2PGE BIT(31)
51 #define EN_L2_WFI_PDN BIT(5)
52 #define EN_PLAT_PDN BIT(4)
58 #define SLPCR_VSTBY BIT(2)
59 #define SLPCR_SBYOS BIT(1)
76 #define SLT_PLAT_PDN BIT(8)
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/arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mq/include/
A Dgpc_reg.h40 #define IRQ_SRC_C1 BIT(29)
41 #define IRQ_SRC_C0 BIT(28)
42 #define IRQ_SRC_C3 BIT(23)
43 #define IRQ_SRC_C2 BIT(22)
50 #define L2PGE BIT(31)
51 #define EN_L2_WFI_PDN BIT(5)
52 #define EN_PLAT_PDN BIT(4)
54 #define SLPCR_EN_DSM BIT(31)
55 #define SLPCR_RBC_EN BIT(30)
58 #define SLPCR_VSTBY BIT(2)
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/arm-trusted-firmware-2.8.0/plat/brcm/board/stingray/include/
A Dusb_phy.h23 #define DRDU2_U2PLL_LOCK BIT(6U)
24 #define DRDU2_U2PLL_RESETB BIT(5U)
27 #define DRDU2_U2PLL_SUSPEND_EN BIT(0U)
30 #define DRDU2_U2IDDQ BIT(30U)
31 #define DRDU2_U2SOFT_RST_N BIT(29U)
32 #define DRDU2_U2PHY_ON_FLAG BIT(22U)
35 #define DRDU2_U2PHY_RESETB BIT(5U)
36 #define DRDU2_U2PHY_ISO BIT(4U)
37 #define DRDU2_U2AFE_BG_PWRDWNB BIT(3U)
38 #define DRDU2_U2AFE_PLL_PWRDWNB BIT(2U)
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/arm-trusted-firmware-2.8.0/drivers/imx/usdhc/
A Dimx_usdhc.h39 #define XFERTYPE_RSPTYP_48_BUSY (BIT(16) | BIT(17))
42 #define PSTATE_DAT0 BIT(24)
43 #define PSTATE_DLA BIT(2)
44 #define PSTATE_CDIHB BIT(1)
45 #define PSTATE_CIHB BIT(0)
48 #define PROTCTRL_LE BIT(5)
64 #define INTSTAT_DCE BIT(21)
66 #define INTSTAT_CIE BIT(19)
70 #define INTSTAT_BGE BIT(2)
71 #define INTSTAT_TC BIT(1)
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/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/include/
A Dmcucfg.h30 #define sw_spark_en BIT(0)
32 #define sw_fsm_override BIT(2)
35 #define sw_logic_pdb BIT(5)
36 #define sw_iso BIT(6)
39 #define sw_clk_dis BIT(14)
40 #define sw_ckiso BIT(15)
44 #define sw_pwr_on BIT(24)
45 #define sw_coq_dis BIT(25)
71 #define cpu_sw_iso BIT(6)
75 #define cpu_sw_ckiso BIT(10)
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/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/include/
A Dmcucfg.h30 #define sw_spark_en BIT(0)
32 #define sw_fsm_override BIT(2)
35 #define sw_logic_pdb BIT(5)
36 #define sw_iso BIT(6)
39 #define sw_clk_dis BIT(14)
40 #define sw_ckiso BIT(15)
44 #define sw_pwr_on BIT(24)
45 #define sw_coq_dis BIT(25)
71 #define cpu_sw_iso BIT(6)
75 #define cpu_sw_ckiso BIT(10)
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/arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/include/
A Dmcucfg.h30 #define sw_spark_en BIT(0)
32 #define sw_fsm_override BIT(2)
35 #define sw_logic_pdb BIT(5)
36 #define sw_iso BIT(6)
39 #define sw_clk_dis BIT(14)
40 #define sw_ckiso BIT(15)
44 #define sw_pwr_on BIT(24)
45 #define sw_coq_dis BIT(25)
71 #define cpu_sw_iso BIT(6)
75 #define cpu_sw_ckiso BIT(10)
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/arm-trusted-firmware-2.8.0/plat/brcm/board/stingray/driver/
A Dplat_emmc.c59 val = (BIT(IOPAD_CTRL6_SDIO0_DATA7_SRC_R) | in emmc_soft_reset()
60 BIT(IOPAD_CTRL6_SDIO0_DATA7_HYS_R) | in emmc_soft_reset()
62 BIT(IOPAD_CTRL6_SDIO0_DATA6_SRC_R) | in emmc_soft_reset()
63 BIT(IOPAD_CTRL6_SDIO0_DATA6_HYS_R) | in emmc_soft_reset()
68 val = (BIT(IOPAD_CTRL5_SDIO0_DATA3_SRC_R) | in emmc_soft_reset()
69 BIT(IOPAD_CTRL5_SDIO0_DATA3_HYS_R) | in emmc_soft_reset()
71 BIT(IOPAD_CTRL5_SDIO0_DATA4_SRC_R) | in emmc_soft_reset()
72 BIT(IOPAD_CTRL5_SDIO0_DATA4_HYS_R) | in emmc_soft_reset()
95 BIT(IOPAD_CTRL4_SDIO0_CD_SRC_R) | in emmc_soft_reset()
96 BIT(IOPAD_CTRL4_SDIO0_CD_HYS_R)); in emmc_soft_reset()
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/arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/dcm/
A Dmtk_dcm_utils.c12 BIT(17) | \
13 BIT(18) | \
14 BIT(21))
16 BIT(17) | \
17 BIT(18))
21 BIT(21))
24 BIT(18))
389 BIT(4))
425 BIT(3))
429 BIT(3))
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/arm-trusted-firmware-2.8.0/plat/mediatek/drivers/dcm/mt8188/
A Dmtk_dcm_utils.c12 #define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(15) | BIT(16) | BIT(17) | \
13 BIT(18) | BIT(21))
14 #define MP_CPUSYS_TOP_ADB_DCM_REG2_MASK (BIT(15) | BIT(16) | BIT(17) | BIT(18))
16 #define MP_CPUSYS_TOP_ADB_DCM_REG1_ON (BIT(15) | BIT(16) | BIT(17) | \
17 BIT(18) | BIT(21))
18 #define MP_CPUSYS_TOP_ADB_DCM_REG2_ON (BIT(15) | BIT(16) | BIT(17) | BIT(18))
125 #define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON (BIT(11) | BIT(24) | BIT(25))
335 #define MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
337 #define MP_CPUSYS_TOP_MP0_QDCM_REG1_ON (BIT(0) | BIT(1) | BIT(2) | BIT(3))
377 #define CPCCFG_REG_EMI_WFIFO_REG0_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
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/arm-trusted-firmware-2.8.0/drivers/marvell/comphy/
A Dphy-comphy-3700.h47 #define PU_PLL_BIT BIT(14)
48 #define PU_RX_BIT BIT(13)
49 #define PU_TX_BIT BIT(12)
51 #define PU_DFE_BIT BIT(10)
53 #define PLL_LOCK_BIT BIT(8)
111 #define GS2_VREG_RXTX_MAS_ISET_MASK (BIT(7) | BIT(8))
144 #define PRD_TXMARGIN_MASK (BIT(1) | BIT(2) | BIT(3))
146 #define CFG_TX_ALIGN_POS_MASK (BIT(5) | BIT(6) | BIT(7) | BIT(8))
153 #define GEN2_TX_DATA_DLY_MASK (BIT(3) | BIT(4))
183 #define BUNDLE_PERIOD_SCALE_MASK (BIT(2) | BIT(3))
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/arm-trusted-firmware-2.8.0/drivers/renesas/rcar/pfc/E3/
A Dpfc_init_e3.c16 #define GPSR0_D15 BIT(15)
22 #define GPSR0_D9 BIT(9)
23 #define GPSR0_D8 BIT(8)
24 #define GPSR0_D7 BIT(7)
25 #define GPSR0_D6 BIT(6)
26 #define GPSR0_D5 BIT(5)
27 #define GPSR0_D4 BIT(4)
28 #define GPSR0_D3 BIT(3)
29 #define GPSR0_D2 BIT(2)
30 #define GPSR0_D1 BIT(1)
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/arm-trusted-firmware-2.8.0/drivers/renesas/rzg/pfc/G2E/
A Dpfc_init_g2e.c19 #define GPSR0_D15 BIT(15)
25 #define GPSR0_D9 BIT(9)
26 #define GPSR0_D8 BIT(8)
27 #define GPSR0_D7 BIT(7)
28 #define GPSR0_D6 BIT(6)
29 #define GPSR0_D5 BIT(5)
30 #define GPSR0_D4 BIT(4)
31 #define GPSR0_D3 BIT(3)
32 #define GPSR0_D2 BIT(2)
33 #define GPSR0_D1 BIT(1)
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/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/dcm/
A Dmtk_dcm_utils.c13 BIT(16) | \
14 BIT(17) | \
15 BIT(18) | \
16 BIT(21))
18 BIT(16) | \
19 BIT(17) | \
20 BIT(18))
23 BIT(16) | \
24 BIT(17) | \
26 BIT(21))
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1234567891011