Searched refs:BIT_SEL_APU_DIV2 (Results 1 – 2 of 2) sorted by relevance
| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/apusys/ |
| A D | apupwr_clkctl.c | 51 { APU_ACC_CONFG_SET0, BIT(BIT_SEL_APU_DIV2) },
54 { APU_ACC_CONFG_SET7, BIT(BIT_SEL_APU_DIV2) },
57 { APU_ACC_CONFG_SET1, BIT(BIT_SEL_APU_DIV2) },
61 { APU_ACC_CONFG_SET2, BIT(BIT_SEL_APU_DIV2) },
64 { APU_ACC_CONFG_SET4, BIT(BIT_SEL_APU_DIV2) },
68 { APU_ACC_CONFG_SET5, BIT(BIT_SEL_APU_DIV2) },
154 apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_clr); in apupwr_smc_acc_set_parent()
175 apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_clr); in apupwr_smc_acc_set_parent()
190 apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_clr); in apupwr_smc_acc_set_parent()
254 apupwr_writel(BIT(BIT_SEL_APU_DIV2), acc_set0); in apupwr_smc_pll_set_rate()
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| A D | apupwr_clkctl_def.h | 190 #define BIT_SEL_APU_DIV2 (10) macro
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