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Searched refs:BL1_RW_BASE (Results 1 – 22 of 22) sorted by relevance

/arm-trusted-firmware-2.8.0/bl1/
A Dbl1.ld.S24 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE
94 . = BL1_RW_BASE; define
95 ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
A Dbl1_main.c48 assert(BL1_RW_BASE > bl1_mem_layout->total_base); in bl1_calc_bl2_mem_layout()
50 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; in bl1_calc_bl2_mem_layout()
/arm-trusted-firmware-2.8.0/plat/hisilicon/poplar/include/
A Dpoplar_layout.h121 #define BL1_RW_BASE (LLOADER_TEXT_BASE + BL1_RW_OFFSET) macro
122 #define BL1_RW_LIMIT (BL1_RW_BASE + BL1_RW_SIZE)
/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey960/aarch64/
A Dhikey960_common.c29 #define MAP_BL1_RW MAP_REGION_FLAT(BL1_RW_BASE, \
30 BL1_RW_LIMIT - BL1_RW_BASE, \
/arm-trusted-firmware-2.8.0/include/plat/marvell/armada/a3k/common/
A Dmarvell_def.h148 #define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \ macro
173 #define BL31_PROGBITS_LIMIT BL1_RW_BASE
/arm-trusted-firmware-2.8.0/include/plat/marvell/armada/a8k/common/
A Dmarvell_def.h179 #define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \ macro
208 #define BL31_PROGBITS_LIMIT BL1_RW_BASE
/arm-trusted-firmware-2.8.0/plat/arm/board/a5ds/include/
A Dplatform_def.h221 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ macro
233 #define BL2_BASE (BL1_RW_BASE - A5DS_MAX_BL2_SIZE)
234 #define BL2_LIMIT BL1_RW_BASE
/arm-trusted-firmware-2.8.0/plat/arm/board/fvp_ve/include/
A Dplatform_def.h204 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ macro
218 #define BL2_BASE (BL1_RW_BASE - FVP_VE_MAX_BL2_SIZE)
219 #define BL2_LIMIT BL1_RW_BASE
/arm-trusted-firmware-2.8.0/include/plat/arm/common/
A Darm_def.h344 BL1_RW_BASE, \
345 BL1_RW_LIMIT - BL1_RW_BASE, \
537 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ macro
547 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE)
574 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
575 #define BL2_LIMIT BL1_RW_BASE
/arm-trusted-firmware-2.8.0/plat/qemu/qemu_sbsa/include/
A Dplatform_def.h118 #define BL1_RW_BASE (BL1_RW_LIMIT - BL1_SIZE) macro
139 #define BL31_LIMIT (BL1_RW_BASE)
140 #define BL31_PROGBITS_LIMIT BL1_RW_BASE
/arm-trusted-firmware-2.8.0/plat/brcm/board/stingray/include/
A Dplatform_def.h101 #define BL1_RW_BASE (BRCM_BL_RAM_BASE) macro
102 #define BL1_RW_LIMIT (BL1_RW_BASE + 0x12000)
/arm-trusted-firmware-2.8.0/plat/arm/board/fvp_r/
A Dfvp_r_bl1_main.c108 assert(bl1_mem_layout->total_base < BL1_RW_BASE); in bl1_calc_bl2_mem_layout()
110 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; in bl1_calc_bl2_mem_layout()
/arm-trusted-firmware-2.8.0/plat/rpi/rpi3/include/
A Dplatform_def.h171 #define BL1_RW_BASE (BL1_RW_LIMIT - PLAT_MAX_BL1_RW_SIZE) macro
195 #define BL31_PROGBITS_LIMIT BL1_RW_BASE
/arm-trusted-firmware-2.8.0/plat/qemu/qemu/include/
A Dplatform_def.h131 #define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000) macro
151 #define BL31_PROGBITS_LIMIT BL1_RW_BASE
/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey/include/
A Dhikey_layout.h40 #define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_8000 */ macro
/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey960/include/
A Dplatform_def.h54 #define BL1_RW_BASE (BL1_RO_LIMIT) /* 1AC2_0000 */ macro
/arm-trusted-firmware-2.8.0/plat/hisilicon/poplar/
A Dbl1_plat_setup.c76 bl1_tzram_layout.total_base = BL1_RW_BASE; in bl1_early_platform_setup()
/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey/
A Dhikey_bl1_setup.c55 bl1_tzram_layout.total_base = BL1_RW_BASE; in bl1_early_platform_setup()
/arm-trusted-firmware-2.8.0/plat/intel/soc/common/include/
A Dplatform_def.h125 #define BL1_RW_BASE (0xffe10000) macro
/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey960/
A Dhikey960_bl1_setup.c87 bl1_tzram_layout.total_base = BL1_RW_BASE; in bl1_early_platform_setup()
/arm-trusted-firmware-2.8.0/docs/design/
A Dfirmware-design.rst147 to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``.
/arm-trusted-firmware-2.8.0/docs/getting_started/
A Dporting-guide.rst191 - **#define : BL1_RW_BASE**

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