| /arm-trusted-firmware-2.8.0/plat/brcm/board/stingray/include/ |
| A D | platform_def.h | 112 #define BL2_BASE QSPI_BASE_ADDR macro
113 #define BL2_LIMIT (BL2_BASE + 0x40000)
118 #define BL2_BASE NAND_BASE_ADDR macro
119 #define BL2_LIMIT (BL2_BASE + 0x40000)
124 #define BL2_BASE (BL1_RW_LIMIT + PAGE_SIZE) macro
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| /arm-trusted-firmware-2.8.0/tools/nxp/create_pbl/ |
| A D | pbl_ch2.mk | 25 …BL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE}\
46 …L} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE} \
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| A D | pbl_ch3.mk | 33 …BL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE}\
62 …L} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE} \
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| /arm-trusted-firmware-2.8.0/include/plat/arm/css/common/ |
| A D | css_def.h | 184 #define SCP_BL2_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE)
185 #define SCP_BL2_LIMIT BL2_BASE
187 #define SCP_BL2U_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE)
188 #define SCP_BL2U_LIMIT BL2_BASE
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| /arm-trusted-firmware-2.8.0/bl2/ |
| A D | bl2.ld.S | 15 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
21 . = BL2_BASE; define
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| A D | bl2_el3.ld.S | 19 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
39 . = BL2_BASE; define
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| /arm-trusted-firmware-2.8.0/include/drivers/arm/css/ |
| A D | css_scp.h | 45 CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
46 CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
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| /arm-trusted-firmware-2.8.0/plat/renesas/common/include/ |
| A D | platform_def.h | 115 #define BL2_BASE U(0xE6304000) macro
118 #define BL2_BASE U(0xE6344000) macro
121 #define BL2_BASE U(0xE6304000) macro
124 #define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE)
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| /arm-trusted-firmware-2.8.0/include/plat/common/ |
| A D | common_def.h | 71 .image_info.image_base = BL2_BASE, \
72 .image_info.image_max_size = BL2_LIMIT - BL2_BASE,\
75 .ep_info.pc = BL2_BASE, \
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| /arm-trusted-firmware-2.8.0/plat/hisilicon/poplar/include/ |
| A D | poplar_layout.h | 125 #define BL2_BASE (LLOADER_TEXT_BASE + BL2_OFFSET) macro
126 #define BL2_LIMIT (BL2_BASE + BL2_SIZE)
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| /arm-trusted-firmware-2.8.0/plat/socionext/uniphier/include/ |
| A D | platform_def.h | 53 #define BL2_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL2_OFFSET) macro
54 #define BL2_LIMIT (BL2_BASE + UNIPHIER_BL2_MAX_SIZE)
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| /arm-trusted-firmware-2.8.0/bl1/tbbr/ |
| A D | tbbr_img_desc.c | 17 .image_info.image_base = BL2_BASE,
18 .image_info.image_max_size = BL2_LIMIT - BL2_BASE,
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| /arm-trusted-firmware-2.8.0/plat/hisilicon/hikey960/include/ |
| A D | platform_def.h | 61 #define BL2_BASE (0x1AC00000) macro
62 #define BL2_LIMIT (BL2_BASE + 0x58000) /* 1AC5_8000 */
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| /arm-trusted-firmware-2.8.0/plat/nxp/common/plat_make_helper/ |
| A D | soc_common_def.mk | 50 ifneq (${BL2_BASE},)
51 $(eval $(call add_define_val,BL2_BASE,${BL2_BASE}))
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| /arm-trusted-firmware-2.8.0/plat/hisilicon/poplar/ |
| A D | bl1_plat_setup.c | 56 bl2_tzram_layout.total_base = BL2_BASE; in bl1_plat_handle_post_image_load()
57 bl2_tzram_layout.total_size = BL32_LIMIT - BL2_BASE; in bl1_plat_handle_post_image_load()
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| /arm-trusted-firmware-2.8.0/include/plat/arm/common/ |
| A D | arm_def.h | 559 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ macro
564 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ macro
574 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) macro
593 #define BL31_NOBITS_BASE BL2_BASE
611 #define BL31_PROGBITS_LIMIT BL2_BASE
617 #define BL31_LIMIT BL2_BASE
652 # define BL32_PROGBITS_LIMIT BL2_BASE
723 #define BL2U_BASE BL2_BASE
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1028a/ |
| A D | soc.def | 64 BL2_BASE := $(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc))
66 # BL2_HDR_LOC is at (BL2_BASE + NXP_ROM_RSVD)
68 # overalp with BL2_BASE
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| /arm-trusted-firmware-2.8.0/drivers/arm/css/scp/ |
| A D | css_bom_bootloader.c | 56 CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
57 CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1088a/ls1088aqds/ |
| A D | plat_def.h | 44 #define BL2_NOLOAD_LIMIT BL2_BASE
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1088a/ls1088ardb/ |
| A D | plat_def.h | 44 #define BL2_NOLOAD_LIMIT BL2_BASE
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| /arm-trusted-firmware-2.8.0/plat/intel/soc/agilex/ |
| A D | bl2_plat_setup.c | 96 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, in bl2_el3_plat_arch_setup()
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| /arm-trusted-firmware-2.8.0/plat/intel/soc/stratix10/ |
| A D | bl2_plat_setup.c | 95 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, in bl2_el3_plat_arch_setup()
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| /arm-trusted-firmware-2.8.0/bl2/aarch64/ |
| A D | bl2_el3_entrypoint.S | 19 #define FIXUP_SIZE ((BL2_LIMIT) - (BL2_BASE))
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| /arm-trusted-firmware-2.8.0/plat/socionext/synquacer/include/ |
| A D | platform_def.h | 64 #define BL2_BASE 0x04000000 macro
66 #define BL2_LIMIT (BL2_BASE + BL2_SIZE)
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1088a/ |
| A D | soc.def | 61 # BL2_BASE=OCRAM_START_ADDR+NXP_ROM_RSVD
62 BL2_BASE := 0x1800a000
|