1 /*
2  * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef CORTEX_A72_H
8 #define CORTEX_A72_H
9 
10 #include <lib/utils_def.h>
11 
12 /* Cortex-A72 midr for revision 0 */
13 #define CORTEX_A72_MIDR		U(0x410FD080)
14 
15 /*******************************************************************************
16  * CPU Extended Control register specific definitions.
17  ******************************************************************************/
18 #define CORTEX_A72_ECTLR				p15, 1, c15
19 
20 #define CORTEX_A72_ECTLR_SMP_BIT			(ULL(1) << 6)
21 #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT		(ULL(1) << 38)
22 #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK		(ULL(0x3) << 35)
23 #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK		(ULL(0x3) << 32)
24 
25 /*******************************************************************************
26  * CPU Memory Error Syndrome register specific definitions.
27  ******************************************************************************/
28 #define CORTEX_A72_MERRSR				p15, 2, c15
29 
30 /*******************************************************************************
31  * CPU Auxiliary Control register specific definitions.
32  ******************************************************************************/
33 #define CORTEX_A72_CPUACTLR				p15, 0, c15
34 
35 #define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH	(ULL(1) << 56)
36 #define CORTEX_A72_CPUACTLR_DIS_LOAD_PASS_STORE		(ULL(1) << 55)
37 #define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA		(ULL(1) << 49)
38 #define CORTEX_A72_CPUACTLR_DCC_AS_DCCI			(ULL(1) << 44)
39 #define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH		(ULL(1) << 32)
40 
41 /*******************************************************************************
42  * L2 Control register specific definitions.
43  ******************************************************************************/
44 #define CORTEX_A72_L2CTLR				p15, 1, c9, c0, 2
45 
46 #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT	U(0)
47 #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT		U(6)
48 
49 #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES		U(0x2)
50 #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES		U(0x1)
51 #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES		U(0x2)
52 
53 /*******************************************************************************
54  * L2 Memory Error Syndrome register specific definitions.
55  ******************************************************************************/
56 #define CORTEX_A72_L2MERRSR				p15, 3, c15
57 
58 #endif /* CORTEX_A72_H */
59