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Searched refs:CPG_PLL0CR (Results 1 – 3 of 3) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/renesas/common/include/
A Drcar_def.h228 #define CPG_PLL0CR (CPG_BASE + 0x00D8U) macro
/arm-trusted-firmware-2.8.0/plat/renesas/rzg/
A Dbl2_plat_setup.c937 reg = mmio_read_32(CPG_PLL0CR); in bl2_el3_early_platform_setup()
939 mmio_write_32(CPG_PLL0CR, reg); in bl2_el3_early_platform_setup()
/arm-trusted-firmware-2.8.0/plat/renesas/rcar/
A Dbl2_plat_setup.c1098 reg = mmio_read_32(CPG_PLL0CR); in bl2_el3_early_platform_setup()
1100 mmio_write_32(CPG_PLL0CR, reg); in bl2_el3_early_platform_setup()

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