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Searched refs:CPG_PLLECR (Results 1 – 5 of 5) sorted by relevance

/arm-trusted-firmware-2.8.0/drivers/renesas/common/ddr/ddr_b/
A Dboot_init_dram_regdef.h39 #define CPG_PLLECR (CPG_BASE + 0x00D0U) macro
A Dboot_init_dram.c393 data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT; in pll3_control()
394 cpg_write_32(CPG_PLLECR, data_l); in pll3_control()
410 data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); in pll3_control()
411 cpg_write_32(CPG_PLLECR, data_l); in pll3_control()
415 data_l = mmio_read_32(CPG_PLLECR); in pll3_control()
434 data_l = mmio_read_32(CPG_PLLECR); in pll3_control()
450 data_l = mmio_read_32(CPG_PLLECR); in pll3_control()
476 data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); in pll3_control()
477 cpg_write_32(CPG_PLLECR, data_l); in pll3_control()
481 data_l = mmio_read_32(CPG_PLLECR); in pll3_control()
/arm-trusted-firmware-2.8.0/drivers/renesas/common/
A Dddr_regs.h247 #define CPG_PLLECR (CPG_BASE + 0x00D0U) macro
/arm-trusted-firmware-2.8.0/drivers/renesas/common/ddr/ddr_a/
A Dddr_init_e3.c70 while (!(mmio_read_32(CPG_PLLECR) & BIT(11))) in init_ddr()
873 while (!(mmio_read_32(CPG_PLLECR) & BIT(11))) in recovery_from_backup_mode()
A Dddr_init_d3.c369 while (!(mmio_read_32(CPG_PLLECR) & BIT(11))) in init_ddr_d3_1600()

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