Searched refs:CPU0 (Results 1 – 16 of 16) sorted by relevance
| /arm-trusted-firmware-2.8.0/plat/intel/soc/common/soc/ |
| A D | socfpga_firewall.c | 105 mmio_clrbits_32(SOCFPGA_CCU_NOC(CPU0, RAM0), in enable_ns_ocram_access()
119 mmio_setbits_32(SOCFPGA_CCU_NOC(CPU0, RAM0), in enable_ocram_firewall()
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| /arm-trusted-firmware-2.8.0/fdts/ |
| A D | morello-fvp.dts | 35 cpu = <&CPU0>;
50 CPU0: cpu0@0 { label
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| A D | tc.dts | 30 cpu = <&CPU0>;
106 CPU0:cpu@0 { label
525 cpu = <&CPU0>;
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| A D | fvp-defs.dtsi | 53 CPU0:cpu@0 { \ label
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| /arm-trusted-firmware-2.8.0/docs/plat/ |
| A D | meson-axg.rst | 11 - Basic PSCI support (CPU_ON, CPU_OFF, SYSTEM_RESET, SYSTEM_OFF). Note that CPU0
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| A D | meson-g12a.rst | 11 - Basic PSCI support (CPU_ON, CPU_OFF, SYSTEM_RESET, SYSTEM_OFF). Note that CPU0
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| A D | meson-gxbb.rst | 11 - Basic PSCI support (CPU_ON, CPU_OFF, SYSTEM_RESET, SYSTEM_OFF). Note that CPU0
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| A D | meson-gxl.rst | 11 - Basic PSCI support (CPU_ON, CPU_OFF, SYSTEM_RESET, SYSTEM_OFF). Note that CPU0
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| A D | poplar.rst | 116 LOADER: CPU0 executes at 0x000ce000
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| /arm-trusted-firmware-2.8.0/plat/arm/board/tc/fdts/ |
| A D | tc_spmc_manifest.dts | 59 CPU0:cpu@0 { label
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| A D | tc_spmc_optee_sp_manifest.dts | 58 CPU0:cpu@0 { label
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| /arm-trusted-firmware-2.8.0/plat/marvell/armada/a8k/common/ |
| A D | plat_pm.c | 68 CPU0, enumerator
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| /arm-trusted-firmware-2.8.0/docs/design/ |
| A D | psci-pd-tree.rst | 248 CPU0 | 3 | |
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| A D | firmware-design.rst | 2157 CPU0 updates its per-CPU field with data cache enabled. This write updates a
2162 the update made by CPU0 as well.
2199 | Lock_0 | for CPU0
2202 | Lock_1 | for CPU0
2207 | Lock_N | for CPU0
2232 operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1
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| /arm-trusted-firmware-2.8.0/docs/getting_started/ |
| A D | porting-guide.rst | 2234 - Target all secure SPIs to CPU0.
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| /arm-trusted-firmware-2.8.0/docs/ |
| A D | change-log.md | 4423 - mediatek: mt8183: Fix AARCH64 init fail on CPU0
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