1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PMU_H__ 8 #define __PMU_H__ 9 10 /* Needed aligned 16 bytes for sp stack top */ 11 #define PSRAM_SP_TOP ((PMUSRAM_BASE + PMUSRAM_RSIZE) & ~0xf) 12 13 /***************************************************************************** 14 * pmu con,reg 15 *****************************************************************************/ 16 #define PMU_WKUP_CFG0_LO 0x00 17 #define PMU_WKUP_CFG0_HI 0x04 18 #define PMU_WKUP_CFG1_LO 0x08 19 #define PMU_WKUP_CFG1_HI 0x0c 20 #define PMU_WKUP_CFG2_LO 0x10 21 22 #define PMU_PWRDN_CON 0x18 23 #define PMU_PWRDN_ST 0x20 24 25 #define PMU_PWRMODE_CORE_LO 0x24 26 #define PMU_PWRMODE_CORE_HI 0x28 27 #define PMU_PWRMODE_COMMON_CON_LO 0x2c 28 #define PMU_PWRMODE_COMMON_CON_HI 0x30 29 30 #define PMU_SFT_CON 0x34 31 #define PMU_INT_ST 0x44 32 #define PMU_BUS_IDLE_REQ 0x64 33 #define PMU_BUS_IDLE_ST 0x6c 34 35 #define PMU_OSC_CNT_LO 0x74 36 #define PMU_OSC_CNT_HI 0x78 37 #define PMU_PLLLOCK_CNT_LO 0x7c 38 #define PMU_PLLLOCK_CNT_HI 0x80 39 #define PMU_PLLRST_CNT_LO 0x84 40 #define PMU_PLLRST_CNT_HI 0x88 41 #define PMU_STABLE_CNT_LO 0x8c 42 #define PMU_STABLE_CNT_HI 0x90 43 #define PMU_WAKEUP_RST_CLR_LO 0x9c 44 #define PMU_WAKEUP_RST_CLR_HI 0xa0 45 46 #define PMU_DDR_SREF_ST 0xa4 47 48 #define PMU_SYS_REG0_LO 0xa8 49 #define PMU_SYS_REG0_HI 0xac 50 #define PMU_SYS_REG1_LO 0xb0 51 #define PMU_SYS_REG1_HI 0xb4 52 #define PMU_SYS_REG2_LO 0xb8 53 #define PMU_SYS_REG2_HI 0xbc 54 #define PMU_SYS_REG3_LO 0xc0 55 #define PMU_SYS_REG3_HI 0xc4 56 57 #define PMU_SCU_PWRDN_CNT_LO 0xc8 58 #define PMU_SCU_PWRDN_CNT_HI 0xcc 59 #define PMU_SCU_PWRUP_CNT_LO 0xd0 60 #define PMU_SCU_PWRUP_CNT_HI 0xd4 61 62 #define PMU_TIMEOUT_CNT_LO 0xd8 63 #define PMU_TIMEOUT_CNT_HI 0xdc 64 65 #define PMU_CPUAPM_CON(cpu) (0xe0 + (cpu) * 0x4) 66 67 #define CORES_PM_DISABLE 0x0 68 #define CLST_CPUS_MSK 0xf 69 70 #define PD_CTR_LOOP 500 71 #define PD_CHECK_LOOP 500 72 #define WFEI_CHECK_LOOP 500 73 #define BUS_IDLE_LOOP 1000 74 75 enum pmu_wkup_cfg2 { 76 pmu_cluster_wkup_en = 0, 77 pmu_gpio_wkup_en = 2, 78 pmu_sdio_wkup_en = 3, 79 pmu_sdmmc_wkup_en = 4, 80 pmu_uart0_wkup_en = 5, 81 pmu_timer_wkup_en = 6, 82 pmu_usbdev_wkup_en = 7, 83 pmu_sft_wkup_en = 8, 84 pmu_timeout_wkup_en = 10, 85 }; 86 87 enum pmu_powermode_core_lo { 88 pmu_global_int_dis = 0, 89 pmu_core_src_gt = 1, 90 pmu_cpu0_pd = 3, 91 pmu_clr_core = 5, 92 pmu_scu_pd = 6, 93 pmu_l2_idle = 8, 94 pmu_l2_flush = 9, 95 pmu_clr_bus2main = 10, 96 pmu_clr_peri2msch = 11, 97 }; 98 99 enum pmu_powermode_core_hi { 100 pmu_apll_pd_en = 3, 101 pmu_dpll_pd_en = 4, 102 pmu_cpll_pd_en = 5, 103 pmu_gpll_pd_en = 6, 104 pmu_npll_pd_en = 7, 105 }; 106 107 enum pmu_powermode_common_lo { 108 pmu_mode_en = 0, 109 pmu_ddr_pd_en = 1, 110 pmu_wkup_rst = 3, 111 pmu_pll_pd = 4, 112 pmu_pmu_use_if = 6, 113 pmu_alive_use_if = 7, 114 pmu_osc_dis = 8, 115 pmu_input_clamp = 9, 116 pmu_sref_enter = 10, 117 pmu_ddrc_gt = 11, 118 pmu_ddrio_ret = 12, 119 pmu_ddrio_ret_deq = 13, 120 pmu_clr_pmu = 14, 121 pmu_clr_peri_pmu = 15, 122 }; 123 124 enum pmu_powermode_common_hi { 125 pmu_clr_bus = 0, 126 pmu_clr_mmc = 1, 127 pmu_clr_msch = 2, 128 pmu_clr_nandc = 3, 129 pmu_clr_gmac = 4, 130 pmu_clr_vo = 5, 131 pmu_clr_vi = 6, 132 pmu_clr_gpu = 7, 133 pmu_clr_usb = 8, 134 pmu_clr_vpu = 9, 135 pmu_clr_crypto = 10, 136 pmu_wakeup_begin_cfg = 11, 137 pmu_peri_clk_src_gt = 12, 138 pmu_bus_clk_src_gt = 13, 139 }; 140 141 enum pmu_pd_id { 142 PD_CPU0 = 0, 143 PD_CPU1 = 1, 144 PD_CPU2 = 2, 145 PD_CPU3 = 3, 146 PD_SCU = 4, 147 PD_USB = 5, 148 PD_DDR = 6, 149 PD_SDCARD = 8, 150 PD_CRYPTO = 9, 151 PD_GMAC = 10, 152 PD_MMC_NAND = 11, 153 PD_VPU = 12, 154 PD_VO = 13, 155 PD_VI = 14, 156 PD_GPU = 15, 157 PD_END = 16, 158 }; 159 160 enum pmu_bus_id { 161 BUS_ID_BUS = 0, 162 BUS_ID_BUS2MAIN = 1, 163 BUS_ID_GPU = 2, 164 BUS_ID_CORE = 3, 165 BUS_ID_CRYPTO = 4, 166 BUS_ID_MMC = 5, 167 BUS_ID_GMAC = 6, 168 BUS_ID_VO = 7, 169 BUS_ID_VI = 8, 170 BUS_ID_SDCARD = 9, 171 BUS_ID_USB = 10, 172 BUS_ID_MSCH = 11, 173 BUS_ID_PERI = 12, 174 BUS_ID_PMU = 13, 175 BUS_ID_VPU = 14, 176 BUS_ID_PERI2MSCH = 15, 177 }; 178 179 enum pmu_pd_state { 180 pmu_pd_on = 0, 181 pmu_pd_off = 1 182 }; 183 184 enum pmu_bus_state { 185 bus_active = 0, 186 bus_idle = 1, 187 }; 188 189 enum cores_pm_ctr_mode { 190 core_pwr_pd = 0, 191 core_pwr_wfi = 1, 192 core_pwr_wfi_int = 2 193 }; 194 195 enum pmu_cores_pm_by_wfi { 196 core_pm_en = 0, 197 core_pm_int_wakeup_en, 198 core_pm_dis_int, 199 core_pm_sft_wakeup_en 200 }; 201 202 /***************************************************************************** 203 * pmu_sgrf 204 *****************************************************************************/ 205 #define PMUSGRF_SOC_CON(i) ((i) * 0x4) 206 207 /***************************************************************************** 208 * pmu_grf 209 *****************************************************************************/ 210 #define GPIO0A_IOMUX 0x0 211 #define GPIO0B_IOMUX 0x4 212 #define GPIO0C_IOMUX 0x8 213 #define GPIO0A_PULL 0x10 214 215 #define GPIO0L_SMT 0x38 216 #define GPIO0H_SMT 0x3c 217 218 #define PMUGRF_SOC_CON(i) (0x100 + (i) * 4) 219 220 #define PMUGRF_PVTM_CON0 0x180 221 #define PMUGRF_PVTM_CON1 0x184 222 #define PMUGRF_PVTM_ST0 0x190 223 #define PMUGRF_PVTM_ST1 0x194 224 225 #define PVTM_CALC_CNT 0x200 226 227 #define PMUGRF_OS_REG(n) (0x200 + (n) * 4) 228 229 #define GPIO0A6_IOMUX_MSK (0x3 << 12) 230 #define GPIO0A6_IOMUX_GPIO (0x0 << 12) 231 #define GPIO0A6_IOMUX_RSTOUT (0x1 << 12) 232 #define GPIO0A6_IOMUX_SHTDN (0x2 << 12) 233 234 enum px30_pmugrf_pvtm_con0 { 235 pgrf_pvtm_st = 0, 236 pgrf_pvtm_en = 1, 237 pgrf_pvtm_div = 2, 238 }; 239 240 /***************************************************************************** 241 * pmu_cru 242 *****************************************************************************/ 243 #define CRU_PMU_MODE 0x20 244 #define CRU_PMU_CLKSEL_CON 0x40 245 #define CRU_PMU_CLKSELS_CON(i) (CRU_PMU_CLKSEL_CON + (i) * 4) 246 #define CRU_PMU_CLKSEL_CON_CNT 5 247 #define CRU_PMU_CLKGATE_CON 0x80 248 #define CRU_PMU_CLKGATES_CON(i) (CRU_PMU_CLKGATE_CON + (i) * 4) 249 #define CRU_PMU_CLKGATE_CON_CNT 2 250 #define CRU_PMU_ATCS_CON 0xc0 251 #define CRU_PMU_ATCSS_CON(i) (CRU_PMU_ATCS_CON + (i) * 4) 252 #define CRU_PMU_ATCS_CON_CNT 2 253 254 /***************************************************************************** 255 * pmusgrf 256 *****************************************************************************/ 257 #define PMUSGRF_RSTOUT_EN (0x7 << 10) 258 #define PMUSGRF_RSTOUT_FST 10 259 #define PMUSGRF_RSTOUT_TSADC 11 260 #define PMUSGRF_RSTOUT_WDT 12 261 262 #define PMUGRF_SOC_CON2_US_WMSK (0x1fff << 16) 263 #define PMUGRF_SOC_CON2_MAX_341US 0x1fff 264 #define PMUGRF_SOC_CON2_200US 0x12c0 265 266 #define PMUGRF_FAILSAFE_SHTDN_TSADC BIT(0) 267 #define PMUGRF_FAILSAFE_SHTDN_WDT BIT(1) 268 269 /***************************************************************************** 270 * QOS 271 *****************************************************************************/ 272 #define CPU_AXI_QOS_ID_COREID 0x00 273 #define CPU_AXI_QOS_REVISIONID 0x04 274 #define CPU_AXI_QOS_PRIORITY 0x08 275 #define CPU_AXI_QOS_MODE 0x0c 276 #define CPU_AXI_QOS_BANDWIDTH 0x10 277 #define CPU_AXI_QOS_SATURATION 0x14 278 #define CPU_AXI_QOS_EXTCONTROL 0x18 279 #define CPU_AXI_QOS_NUM_REGS 0x07 280 281 #define CPU_AXI_CPU_QOS_BASE 0xff508000 282 #define CPU_AXI_GPU_QOS_BASE 0xff520000 283 #define CPU_AXI_ISP_128M_QOS_BASE 0xff548000 284 #define CPU_AXI_ISP_RD_QOS_BASE 0xff548080 285 #define CPU_AXI_ISP_WR_QOS_BASE 0xff548100 286 #define CPU_AXI_ISP_M1_QOS_BASE 0xff548180 287 #define CPU_AXI_VIP_QOS_BASE 0xff548200 288 #define CPU_AXI_RGA_RD_QOS_BASE 0xff550000 289 #define CPU_AXI_RGA_WR_QOS_BASE 0xff550080 290 #define CPU_AXI_VOP_M0_QOS_BASE 0xff550100 291 #define CPU_AXI_VOP_M1_QOS_BASE 0xff550180 292 #define CPU_AXI_VPU_QOS_BASE 0xff558000 293 #define CPU_AXI_VPU_R128_QOS_BASE 0xff558080 294 #define CPU_AXI_DCF_QOS_BASE 0xff500000 295 #define CPU_AXI_DMAC_QOS_BASE 0xff500080 296 #define CPU_AXI_CRYPTO_QOS_BASE 0xff510000 297 #define CPU_AXI_GMAC_QOS_BASE 0xff518000 298 #define CPU_AXI_EMMC_QOS_BASE 0xff538000 299 #define CPU_AXI_NAND_QOS_BASE 0xff538080 300 #define CPU_AXI_SDIO_QOS_BASE 0xff538100 301 #define CPU_AXI_SFC_QOS_BASE 0xff538180 302 #define CPU_AXI_SDMMC_QOS_BASE 0xff52c000 303 #define CPU_AXI_USB_HOST_QOS_BASE 0xff540000 304 #define CPU_AXI_USB_OTG_QOS_BASE 0xff540080 305 306 #define PX30_CPU_AXI_SAVE_QOS(array, base) do { \ 307 array[0] = mmio_read_32(base + CPU_AXI_QOS_ID_COREID); \ 308 array[1] = mmio_read_32(base + CPU_AXI_QOS_REVISIONID); \ 309 array[2] = mmio_read_32(base + CPU_AXI_QOS_PRIORITY); \ 310 array[3] = mmio_read_32(base + CPU_AXI_QOS_MODE); \ 311 array[4] = mmio_read_32(base + CPU_AXI_QOS_BANDWIDTH); \ 312 array[5] = mmio_read_32(base + CPU_AXI_QOS_SATURATION); \ 313 array[6] = mmio_read_32(base + CPU_AXI_QOS_EXTCONTROL); \ 314 } while (0) 315 316 #define PX30_CPU_AXI_RESTORE_QOS(array, base) do { \ 317 mmio_write_32(base + CPU_AXI_QOS_ID_COREID, array[0]); \ 318 mmio_write_32(base + CPU_AXI_QOS_REVISIONID, array[1]); \ 319 mmio_write_32(base + CPU_AXI_QOS_PRIORITY, array[2]); \ 320 mmio_write_32(base + CPU_AXI_QOS_MODE, array[3]); \ 321 mmio_write_32(base + CPU_AXI_QOS_BANDWIDTH, array[4]); \ 322 mmio_write_32(base + CPU_AXI_QOS_SATURATION, array[5]); \ 323 mmio_write_32(base + CPU_AXI_QOS_EXTCONTROL, array[6]); \ 324 } while (0) 325 326 #define SAVE_QOS(array, NAME) \ 327 PX30_CPU_AXI_SAVE_QOS(array, CPU_AXI_##NAME##_QOS_BASE) 328 #define RESTORE_QOS(array, NAME) \ 329 PX30_CPU_AXI_RESTORE_QOS(array, CPU_AXI_##NAME##_QOS_BASE) 330 331 #endif /* __PMU_H__ */ 332