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Searched refs:CRF_APB_CLK_BASE (Results 1 – 1 of 1) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/xilinx/zynqmp/include/
A Dzynqmp_def.h42 #define CRF_APB_CLK_BASE U(0xFD1A0020) macro
263 #define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00)
264 #define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c)
265 #define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18)
266 #define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24)
271 #define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40)
273 #define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48)
277 #define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60)
278 #define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64)
279 #define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80)
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