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Searched refs:CRF_APB_VPLL_CTRL (Results 1 – 2 of 2) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/xilinx/zynqmp/include/
A Dzynqmp_def.h265 #define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18) macro
/arm-trusted-firmware-2.8.0/plat/xilinx/zynqmp/pm_service/
A Dpm_api_clock.c977 .control_reg = CRF_APB_VPLL_CTRL,
985 .control_reg = CRF_APB_VPLL_CTRL,
1003 .control_reg = CRF_APB_VPLL_CTRL,
1011 .control_reg = CRF_APB_VPLL_CTRL,
1023 .control_reg = CRF_APB_VPLL_CTRL,
1041 .control_reg = CRF_APB_VPLL_CTRL,

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