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Searched refs:CRL_APB_CLK_BASE (Results 1 – 1 of 1) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/xilinx/zynqmp/include/
A Dzynqmp_def.h56 #define CRL_APB_CLK_BASE U(0xFF5E0020) macro
289 #define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00)
290 #define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10)
291 #define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20)
311 #define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70)
313 #define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80)
314 #define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84)
324 #define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4)
325 #define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc)
326 #define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4)
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