CTLR_ENABLE_G0_BIT (reference) in projects: arm-trusted-firmware-2.8.0

Searched refs:CTLR_ENABLE_G0_BIT (Results 1 – 5 of 5) sorted by relevance

/arm-trusted-firmware-2.8.0/drivers/arm/gic/v2/
A D	gicv2_main.c	`46 val = CTLR_ENABLE_G0_BIT \| FIQ_EN_BIT \| FIQ_BYP_DIS_GRP0; in gicv2_cpuif_enable() 67 val &= ~(CTLR_ENABLE_G0_BIT \| CTLR_ENABLE_G1_BIT); in gicv2_cpuif_disable() 90 if ((ctlr & CTLR_ENABLE_G0_BIT) == 0U) { in gicv2_pcpu_distif_init() 92 ctlr \| CTLR_ENABLE_G0_BIT); in gicv2_pcpu_distif_init() 111 ctlr & ~(CTLR_ENABLE_G0_BIT \| CTLR_ENABLE_G1_BIT)); in gicv2_distif_init() 122 gicd_write_ctlr(driver_data->gicd_base, ctlr \| CTLR_ENABLE_G0_BIT); in gicv2_distif_init()`
/arm-trusted-firmware-2.8.0/drivers/arm/gic/v3/
A D	gic600_multichip.c	`48 (CTLR_ENABLE_G0_BIT \| CTLR_ENABLE_G1S_BIT \| in set_gicd_dchipr_rt_owner() 84 (CTLR_ENABLE_G0_BIT \| CTLR_ENABLE_G1S_BIT \| in set_gicd_chipr_n() 322 (CTLR_ENABLE_G0_BIT \| CTLR_ENABLE_G1S_BIT \| in gic600_multichip_init()`
A D	gicv3_helpers.c	`232 ctlr_enable \|= CTLR_ENABLE_G0_BIT; in gicv3_secure_spis_config_props() 344 ctlr_enable \|= CTLR_ENABLE_G0_BIT; in gicv3_secure_ppi_sgi_config_props()`
A D	gicv3_main.c	`198 CTLR_ENABLE_G0_BIT \| in gicv3_distif_init() 839 CTLR_ENABLE_G0_BIT \| in gicv3_distif_init_restore()`
/arm-trusted-firmware-2.8.0/include/drivers/arm/
A D	gic_common.h	`62 #define CTLR_ENABLE_G0_BIT BIT_32(CTLR_ENABLE_G0_SHIFT) macro`

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