Searched refs:DCFG_DEVDISR5_OFFSET (Results 1 – 7 of 7) sorted by relevance
| /arm-trusted-firmware-2.8.0/include/drivers/nxp/dcfg/ |
| A D | dcfg_lsch3.h | 25 #define DCFG_DEVDISR5_OFFSET 0x80 macro
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| A D | dcfg_lsch2.h | 17 #define DCFG_DEVDISR5_OFFSET 0x080 macro
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1088a/include/ |
| A D | soc.h | 165 #define DCFG_DEVDISR5_OFFSET 0x80 macro
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| /arm-trusted-firmware-2.8.0/drivers/nxp/dcfg/ |
| A D | dcfg.c | 75 reg = gur_in32(dcfg_init_info->g_nxp_dcfg_addr + DCFG_DEVDISR5_OFFSET); in get_devdisr5_info()
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1043a/aarch64/ |
| A D | ls1043a.S | 524 mov x0, #DCFG_DEVDISR5_OFFSET
526 mov x0, #DCFG_DEVDISR5_OFFSET
1200 mov x0, #DCFG_DEVDISR5_OFFSET
1203 mov x0, #DCFG_DEVDISR5_OFFSET
1519 str w4, [x8, #DCFG_DEVDISR5_OFFSET] /* disable ddr cntrlr clk in devdisr5 */
1525 str w4, [x8, #DCFG_DEVDISR5_OFFSET] /* re-enable ddr in devdisr5 */
1552 str w1, [x8, #DCFG_DEVDISR5_OFFSET] /* reset devdisr5 */
1629 str w4, [x8, #DCFG_DEVDISR5_OFFSET] /* disable ddr cntrlr clk in devdisr5 */
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-lx2160a/aarch64/ |
| A D | lx2160a.S | 1150 ldr w17, [x3, #DCFG_DEVDISR5_OFFSET]
1170 str w11, [x3, #DCFG_DEVDISR5_OFFSET]
1229 str w17, [x3, #DCFG_DEVDISR5_OFFSET]
1430 str w9, [x3, #DCFG_DEVDISR5_OFFSET]
1463 str w7, [x3, #DCFG_DEVDISR5_OFFSET]
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1088a/aarch64/ |
| A D | ls1088a.S | 1196 ldr x0, =DCFG_DEVDISR5_OFFSET
1275 ldr x22, =DCFG_DEVDISR5_OFFSET
1767 str w1, [x8, #DCFG_DEVDISR5_OFFSET]
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Completed in 11 milliseconds