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Searched refs:DDR2_SEC_BASE (Results 1 – 3 of 3) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey960/include/
A Dplat.ld.S12 RAM2 (rw): ORIGIN = DDR2_SEC_BASE, LENGTH = DDR2_SEC_SIZE
/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey960/
A Dhikey960_def.h36 #define DDR2_SEC_BASE 0x42C00000 macro
A Dhikey960_bl31_setup.c133 mmap_add_region(DDR2_SEC_BASE, DDR2_SEC_BASE, DDR2_SEC_SIZE, in bl31_plat_arch_setup()

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