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Searched refs:DDRC_DBG1 (Results 1 – 4 of 4) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/
A Dddr4_dvfs.c173 mmio_setbits_32(DDRC_DBG1(0), (0x1 << 1)); in ddr4_swffc()
214 mmio_clrbits_32(DDRC_DBG1(0), (0x1 << 1)); in ddr4_swffc()
A Dlpddr4_dvfs.c141 mmio_setbits_32(DDRC_DBG1(0), 0x1); in lpddr4_swffc()
270 mmio_clrbits_32(DDRC_DBG1(0), 0x1); in lpddr4_swffc()
A Ddram_retention.c142 mmio_write_32(DDRC_DBG1(0), 0x0); in dram_exit_retention()
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/
A Dddrc.h141 #define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304) macro

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