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Searched refs:DDRC_DDR_SS_GPR0 (Results 1 – 2 of 2) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/
A Ddram_retention.c151 mmio_write_32(DDRC_DDR_SS_GPR0, 0x01); /*LPDDR4 mode */ in dram_exit_retention()
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/
A Dddrc.h11 #define DDRC_DDR_SS_GPR0 0x3d000000 macro

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