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Searched refs:DDRC_DFILPCFG0 (Results 1 – 2 of 2) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/
A Dlpddr4_dvfs.c90 val = mmio_read_32(DDRC_DFILPCFG0(0)); in lpddr4_swffc()
92 mmio_write_32(DDRC_DFILPCFG0(0), 0x0); in lpddr4_swffc()
266 mmio_setbits_32(DDRC_DFILPCFG0(0), BIT(8)); in lpddr4_swffc()
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/
A Dddrc.h94 #define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198) macro

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