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Searched refs:DDRC_DFIMISC (Results 1 – 5 of 5) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/
A Ddram_retention.c56 mmio_write_32(DDRC_DFIMISC(0), 0x0); in dram_enter_retention()
58 mmio_write_32(DDRC_DFIMISC(0), 0x1f00); in dram_enter_retention()
59 mmio_write_32(DDRC_DFIMISC(0), 0x1f20); in dram_enter_retention()
65 mmio_write_32(DDRC_DFIMISC(0), 0x1f00); in dram_enter_retention()
155 mmio_write_32(DDRC_DFIMISC(0), 0x0); in dram_exit_retention()
169 mmio_write_32(DDRC_DFIMISC(0), 0x20); in dram_exit_retention()
176 mmio_write_32(DDRC_DFIMISC(0), 0x0); in dram_exit_retention()
178 mmio_write_32(DDRC_DFIMISC(0), 0x1); in dram_exit_retention()
A Dddr4_dvfs.c104 mmio_write_32(DDRC_DFIMISC(0), 0x00000000 | (pstate << 8)); in sw_pstate()
105 mmio_write_32(DDRC_DFIMISC(0), 0x00000020 | (pstate << 8)); in sw_pstate()
115 mmio_write_32(DDRC_DFIMISC(0), 0x00000000 | (pstate << 8)); in sw_pstate()
A Dlpddr4_dvfs.c183 val = mmio_read_32(DDRC_DFIMISC(0)); in lpddr4_swffc()
186 mmio_write_32(DDRC_DFIMISC(0), val); in lpddr4_swffc()
189 mmio_write_32(DDRC_DFIMISC(0), val); in lpddr4_swffc()
200 mmio_clrbits_32(DDRC_DFIMISC(0), 0x20); in lpddr4_swffc()
A Ddram.c135 current_fsp = mmio_read_32(DDRC_DFIMISC(0)) & 0xf; in dram_info_init()
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/
A Dddrc.h99 #define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0) macro

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