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Searched refs:DDRC_DFISTAT (Results 1 – 4 of 4) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/
A Ddram_retention.c61 while (mmio_read_32(DDRC_DFISTAT(0)) & 0x1) { in dram_enter_retention()
67 while (!(mmio_read_32(DDRC_DFISTAT(0)) & 0x1)) { in dram_enter_retention()
171 while (!(mmio_read_32(DDRC_DFISTAT(0)) & 0x1)) { in dram_exit_retention()
A Dddr4_dvfs.c108 while (mmio_read_32(DDRC_DFISTAT(0)) & 0x1) { in sw_pstate()
118 while (!(mmio_read_32(DDRC_DFISTAT(0)) & 0x1)) { in sw_pstate()
A Dlpddr4_dvfs.c94 val = mmio_read_32(DDRC_DFISTAT(0)); // dfi_lp_ack in lpddr4_swffc()
193 val = mmio_read_32(DDRC_DFISTAT(0)); in lpddr4_swffc()
204 val = mmio_read_32(DDRC_DFISTAT(0)); in lpddr4_swffc()
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/
A Dddrc.h102 #define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc) macro

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