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Searched refs:DDRC_FREQ1_ZQCTL0 (Results 1 – 2 of 2) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/
A Dlpddr4_dvfs.c120 mmio_setbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(31)); in lpddr4_swffc()
211 mmio_setbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(30)); in lpddr4_swffc()
241 mmio_clrbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(30)); in lpddr4_swffc()
278 mmio_clrbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(31)); in lpddr4_swffc()
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/
A Dddrc.h228 #define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180) macro

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