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Searched refs:DDRC_MRCTRL0 (Results 1 – 3 of 3) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/
A Dddr4_dvfs.c39 mmio_write_32(DDRC_MRCTRL0(0), mr_type | (mr_mirror << 12) | (rank << 4)); in ddr4_mr_write()
49 mmio_setbits_32(DDRC_MRCTRL0(0), BIT(31)); in ddr4_mr_write()
A Dlpddr4_dvfs.c26 mmio_write_32(DDRC_MRCTRL0(0), (mr_rank << 4)); in lpddr4_mr_write()
28 mmio_setbits_32(DDRC_MRCTRL0(0), BIT(31)); in lpddr4_mr_write()
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/
A Dddrc.h18 #define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10) macro

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