Searched refs:DDRC_PWRCTL (Results 1 – 4 of 4) sorted by relevance
| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/ |
| A D | lpddr4_dvfs.c | 58 mmio_clrbits_32(DDRC_PWRCTL(0), 0xf); in lpddr4_swffc()
124 mmio_clrbits_32(DDRC_PWRCTL(0), 0x1); in lpddr4_swffc()
133 mmio_setbits_32(DDRC_PWRCTL(0), 0x60); in lpddr4_swffc()
154 mmio_clrsetbits_32(DDRC_PWRCTL(0), 0x60, 0x20); in lpddr4_swffc()
218 mmio_clrsetbits_32(DDRC_PWRCTL(0), 0x60, 0x40); in lpddr4_swffc()
256 mmio_clrbits_32(DDRC_PWRCTL(0), 0x40); in lpddr4_swffc()
273 mmio_setbits_32(DDRC_PWRCTL(0), 0x1); in lpddr4_swffc()
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| A D | dram_retention.c | 43 mmio_write_32(DDRC_PWRCTL(0), 0xaa); in dram_enter_retention()
141 mmio_write_32(DDRC_PWRCTL(0), 0xaa); in dram_exit_retention()
187 mmio_write_32(DDRC_PWRCTL(0), 0x88); in dram_exit_retention()
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| A D | ddr4_dvfs.c | 132 mmio_clrbits_32(DDRC_PWRCTL(0), (1 << 5)); in sw_pstate()
200 mmio_setbits_32(DDRC_PWRCTL(0), (1 << 5)); in ddr4_swffc()
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| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/ |
| A D | ddrc.h | 25 #define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30) macro
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