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Searched refs:DDRC_RFSHCTL3 (Results 1 – 4 of 4) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/
A Dddr4_dvfs.c91 val = mmio_read_32(DDRC_RFSHCTL3(0)); in sw_pstate()
93 mmio_write_32(DDRC_RFSHCTL3(0), val & 0xFFFFFFFD); in sw_pstate()
95 mmio_write_32(DDRC_RFSHCTL3(0), val | 0x2); in sw_pstate()
A Dlpddr4_dvfs.c176 val = mmio_read_32(DDRC_RFSHCTL3(0)); in lpddr4_swffc()
178 mmio_write_32(DDRC_RFSHCTL3(0), val); in lpddr4_swffc()
A Ddram_retention.c195 mmio_write_32(DDRC_RFSHCTL3(0), 0x0); in dram_exit_retention()
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/
A Dddrc.h33 #define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60) macro

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