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Searched refs:DDRC_STAT (Results 1 – 4 of 4) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/
A Dlpddr4_dvfs.c95 val2 = mmio_read_32(DDRC_STAT(0)); // operating_mode in lpddr4_swffc()
102 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()
128 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()
137 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()
158 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()
221 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()
261 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()
A Dddr4_dvfs.c134 while ((mmio_read_32(DDRC_STAT(0)) & 0x3f) == 0x23) { in sw_pstate()
192 while ((mmio_read_32(DDRC_STAT(0)) & 0x3) == 0x3) { in ddr4_swffc()
206 while ((mmio_read_32(DDRC_STAT(0)) & 0x3f) != 0x23) { in ddr4_swffc()
A Ddram_retention.c47 while (0x223 != (mmio_read_32(DDRC_STAT(0)) & 0x33f)) { in dram_enter_retention()
51 while (0x23 != (mmio_read_32(DDRC_STAT(0)) & 0x3f)) { in dram_enter_retention()
189 while (0x1 != (mmio_read_32(DDRC_STAT(0)) & 0x7)) { in dram_exit_retention()
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/
A Dddrc.h16 #define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) macro

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