Searched refs:DDRC_SWCTL (Results 1 – 4 of 4) sorted by relevance
| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/ |
| A D | dram_retention.c | 57 mmio_write_32(DDRC_SWCTL(0), 0x0); in dram_enter_retention()
71 mmio_write_32(DDRC_SWCTL(0), 0x1); in dram_enter_retention()
147 mmio_write_32(DDRC_SWCTL(0), 0x0); in dram_exit_retention()
168 mmio_write_32(DDRC_SWCTL(0), 0x0); in dram_exit_retention()
181 mmio_write_32(DDRC_SWCTL(0), 0x1); in dram_exit_retention()
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| A D | ddr4_dvfs.c | 77 mmio_write_32(DDRC_SWCTL(0), 0x0); in sw_pstate()
147 mmio_write_32(DDRC_SWCTL(0), 0x0); in ddr4_swffc()
235 mmio_write_32(DDRC_SWCTL(0), 0x1); in ddr4_swffc()
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| A D | lpddr4_dvfs.c | 165 mmio_write_32(DDRC_SWCTL(0), 0x0000); in lpddr4_swffc()
248 mmio_write_32(DDRC_SWCTL(0), 0x1); in lpddr4_swffc()
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| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/ |
| A D | ddrc.h | 146 #define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320) macro
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