Searched refs:DPLL_ID (Results 1 – 11 of 11) sorted by relevance
| /arm-trusted-firmware-2.8.0/plat/rockchip/px30/drivers/soc/ |
| A D | soc.h | 18 DPLL_ID, enumerator
98 ((id) == DPLL_ID ? 4 : 2 * (id)))
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3328/drivers/pmu/ |
| A D | pmu.c | 301 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(DPLL_ID)); in dpll_suspend()
306 mmio_read_32(CRU_BASE + PLL_CONS(DPLL_ID, i)); in dpll_suspend()
307 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_suspend()
309 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_suspend()
317 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_resume()
319 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_resume()
321 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_resume()
327 if (mmio_read_32(CRU_BASE + PLL_CONS(DPLL_ID, 1)) & in dpll_resume()
337 PLL_NORM_MODE(DPLL_ID)); in dpll_resume()
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3368/drivers/ddr/ |
| A D | ddr_rk3368.c | 390 p_ddr_reg->dpllmodeaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3); in ddr_reg_save()
394 p_ddr_reg->dpllresetaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3); in ddr_reg_save()
397 p_ddr_reg->dpllconaddr = CRU_BASE + PLL_CONS(DPLL_ID, 0); in ddr_reg_save()
401 PLL_CONS(DPLL_ID, 0)) in ddr_reg_save()
405 PLL_CONS(DPLL_ID, 1)) in ddr_reg_save()
408 PLL_CONS(DPLL_ID, 2)) in ddr_reg_save()
411 PLL_CONS(DPLL_ID, 3)) in ddr_reg_save()
419 p_ddr_reg->dplllockaddr = CRU_BASE + PLL_CONS(DPLL_ID, 1); in ddr_reg_save()
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/soc/ |
| A D | soc.c | 171 save_pll(slp_data.plls_con[DPLL_ID], DPLL_ID); in prepare_abpll_for_ddrctrl()
173 restore_pll(ABPLL_ID, slp_data.plls_con[DPLL_ID]); in prepare_abpll_for_ddrctrl()
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| A D | soc.h | 99 DPLL_ID, enumerator
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3328/drivers/soc/ |
| A D | soc.h | 27 DPLL_ID, enumerator
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3288/drivers/soc/ |
| A D | soc.h | 12 DPLL_ID, enumerator
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3368/drivers/soc/ |
| A D | soc.h | 13 DPLL_ID, enumerator
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/dram/ |
| A D | suspend.c | 710 dpll_data[i] = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, i)); in dmc_suspend()
806 pmusram_restore_pll(DPLL_ID, dpll_data); in dmc_resume()
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| A D | dfs.c | 1716 refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f; in ddr_get_rate()
1717 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; in ddr_get_rate()
1719 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7; in ddr_get_rate()
1721 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7; in ddr_get_rate()
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/pmu/ |
| A D | pmu.c | 1298 i <= CRU_PLL_CON(DPLL_ID, 5))) in cru_register_restore()
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Completed in 26 milliseconds