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Searched refs:DRAM_PLL_CTRL (Results 1 – 5 of 5) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/
A Dclock.c87 mmio_setbits_32(DRAM_PLL_CTRL, (1 << 16)); in dram_pll_init()
88 mmio_clrbits_32(DRAM_PLL_CTRL, (1 << 9)); in dram_pll_init()
92 mmio_write_32(DRAM_PLL_CTRL + 0x4, (300 << 12) | (3 << 4) | 2); in dram_pll_init()
95 mmio_write_32(DRAM_PLL_CTRL + 0x4, (400 << 12) | (3 << 4) | 3); in dram_pll_init()
98 mmio_write_32(DRAM_PLL_CTRL + 0x4, (266 << 12) | (3 << 4) | 3); in dram_pll_init()
101 mmio_write_32(DRAM_PLL_CTRL + 0x4, (334 << 12) | (3 << 4) | 4); in dram_pll_init()
107 mmio_setbits_32(DRAM_PLL_CTRL, BIT(9)); in dram_pll_init()
109 while (!(mmio_read_32(DRAM_PLL_CTRL) & BIT(31))) { in dram_pll_init()
114 mmio_clrbits_32(DRAM_PLL_CTRL, BIT(16)); in dram_pll_init()
A Ddram_retention.c24 #define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) macro
128 while (!(mmio_read_32(DRAM_PLL_CTRL) & BIT(31))) { in dram_exit_retention()
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mm/include/
A Dplatform_def.h157 #define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) macro
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mn/include/
A Dplatform_def.h133 #define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) macro
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mp/include/
A Dplatform_def.h169 #define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) macro

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