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Searched refs:DVFSRC_DDR_QOS1 (Results 1 – 6 of 6) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/spm/
A Dmt_spm_vcorefs.h77 #define DVFSRC_DDR_QOS1 (DVFSRC_BASE + 0xA38) macro
A Dmt_spm_vcorefs.c71 { DVFSRC_DDR_QOS1, 0x00000026 },
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/spm/
A Dmt_spm_vcorefs.c36 { DVFSRC_DDR_QOS1, 0x00000026 },
A Dmt_spm_vcorefs.h231 #define DVFSRC_DDR_QOS1 (DVFSRC_BASE + 0xA38) macro
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/spm/
A Dmt_spm_vcorefs.c227 {DVFSRC_DDR_QOS1, 0x00000026},
A Dmt_spm_vcorefs.h217 #define DVFSRC_DDR_QOS1 (DVFSRC_BASE + 0xA38) macro

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