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Searched refs:DVFSRC_DDR_QOS5 (Results 1 – 6 of 6) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/spm/
A Dmt_spm_vcorefs.h119 #define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18) macro
A Dmt_spm_vcorefs.c75 { DVFSRC_DDR_QOS5, 0x00000066 },
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/spm/
A Dmt_spm_vcorefs.c40 { DVFSRC_DDR_QOS5, 0x00000066 },
A Dmt_spm_vcorefs.h303 #define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18) macro
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/spm/
A Dmt_spm_vcorefs.c231 {DVFSRC_DDR_QOS5, 0x00000077},
A Dmt_spm_vcorefs.h289 #define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18) macro

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