ECC (reference) in projects: arm-trusted-firmware-2.8.0

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Searched refs:ECC (Results 1 – 14 of 14) sorted by relevance

/arm-trusted-firmware-2.8.0/include/drivers/nxp/crypto/caam/
A D	caam.h	`27 ECC enumerator`
/arm-trusted-firmware-2.8.0/drivers/nxp/crypto/caam/src/auth/
A D	nxp_crypto.c	`56 case ECC: in verify_signature()`
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1088a/
A D	soc.def	`86 # OCRAM ECC Enabled`
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1028a/
A D	soc.def	`96 # OCRAM ECC Enabled`
/arm-trusted-firmware-2.8.0/docs/plat/
A D	intel-agilex.rst	`72 INFO: ECC is disabled.`
A D	intel-stratix10.rst	`72 INFO: ECC is disabled.`
A D	nvidia-tegra.rst	`129 /* L2 ECC parity protection disable flag \*/ 146 - 'tegra\_enable\_l2\_ecc\_parity\_prot': This flag enables the L2 ECC and Parity`
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1043a/
A D	soc.def	`106 # OCRAM ECC Enabled`
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1046a/
A D	soc.def	`106 # OCRAM ECC Enabled`
/arm-trusted-firmware-2.8.0/docs/components/
A D	rmm-el3-comms-spec.rst	`427 Supported ECC Curves 434 0,ECC SECP384R1`
/arm-trusted-firmware-2.8.0/docs/plat/nxp/
A D	nxp-layerscape.rst	`103 Arm Cortex-A72 cores with ECC-protected L1 and L2 cache memories for high`
/arm-trusted-firmware-2.8.0/docs/plat/marvell/armada/
A D	build.rst	`395 In order to work in 32bit DDR, instead of the default 64bit ECC DDR,`
/arm-trusted-firmware-2.8.0/docs/
A D	change-log.md	`1676 …- fix ECC Double Bit Error handling ([c703d75](https://review.trustedfirmware.org/plugins/gitiles/… 3766 - Added support for DDR with 32-bit bus width (both ECC and non-ECC) 4541 - arm/n1sdp: Add code for DDR ECC enablement and BL33 copy to DDR, Initialise`
/arm-trusted-firmware-2.8.0/docs/getting_started/
A D	porting-guide.rst	`2315 sign Realm attestation token. The API currently only supports P-384 ECC curve`

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