| /arm-trusted-firmware-2.8.0/docs/design/ |
| A D | interrupt-framework-design.rst | 37 context. It is always handled in Secure-EL1.
40 Secure-EL1, Non-secure EL1 or EL2 depending upon the security state of the
95 Secure-EL1 interrupts
104 handover the interrupt to Secure-EL1 for handling.
211 handled in Secure-EL1. They can be delivered to Secure-EL1 via EL3 but they
292 which runs only in Secure-EL1.
527 Secure payload IHF design w.r.t secure-EL1 interrupts
531 triggered at one of the Secure-EL1 FIQ exception vectors. The Secure-EL1
551 Secure-EL1 IHF should then handle all Secure-EL1 interrupt through the
558 triggered at one of the Secure-EL1 IRQ exception vectors . The Secure-EL1
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| A D | firmware-design.rst | 56 - Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional)
277 disable AArch32 Secure self-hosted privileged debug from S-EL1.
438 AArch64 BL32 (Secure-EL1 Payload) image load
603 AArch64 BL32 (Secure-EL1 Payload) image initialization
868 #. Secure-EL1 Payload Dispatcher service
870 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then
872 context between the normal world (EL1/EL2) and trusted world (Secure-EL1).
1081 Secure-EL1 Payloads and Dispatchers
1092 the *Secure-EL1 Payload* - as it is not always a Trusted OS.
1094 TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload
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| /arm-trusted-firmware-2.8.0/docs/security_advisories/ |
| A D | security-advisory-tfv-3.rst | 5 | Title | RO memory is always executable at AArch64 Secure EL1 |
15 | Affected | executing at AArch64 Secure EL1 |
34 This feature does not work correctly for AArch64 images executing at Secure EL1.
58 determine whether a region is executable. The Secure EL1&0 translation regime
61 in the Secure EL1&0 regime. As a result, this programs the Secure EL0 execution
62 permissions but always leaves the memory as executable at Secure EL1.
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| A D | security-advisory-tfv-2.rst | 43 meaning that debug exceptions from Secure EL1 are enabled by the authentication
44 interface. Therefore this issue only exists for AArch32 Secure EL1 code when
50 from AArch32 Secure EL1.
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| A D | security-advisory-tfv-6.rst | 53 Secure-EL1 and executing the ``BPIALL`` instruction. This workaround is
75 disable/enable" and "BPIALL at AArch32 Secure-EL1" workarounds described above.
80 at invalidating the branch predictor on Cortex-A57, the drop into Secure-EL1
97 | ``PSCI_VERSION`` with "BPIALL at AArch32 Secure-EL1" | 1276 |
99 | ``SMCCC_ARCH_WORKAROUND_1`` with "BPIALL at AArch32 Secure-EL1" | 770 |
131 translation regime, for example between EL0 and EL1, therefore this variant
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| A D | security-advisory-tfv-5.rst | 39 transitioning to S-EL1.
50 NOTE: The original pull request referenced above only fixed the issue for S-EL1
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| /arm-trusted-firmware-2.8.0/docs/components/spd/ |
| A D | optee-dispatcher.rst | 4 `OP-TEE OS`_ is a Trusted OS running as Secure EL1.
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| A D | tlk-dispatcher.rst | 20 TLK is a Trusted OS running as Secure EL1. It is a Free Open Source Software
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| /arm-trusted-firmware-2.8.0/plat/arm/board/fvp/fdts/ |
| A D | optee_sp_manifest.dts | 22 exception-level = <2>; /* S-EL1 */
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| /arm-trusted-firmware-2.8.0/docs/components/ |
| A D | secure-partition-manager.rst | 112 S-EL1 or S-EL2:
141 SPMC located at S-EL1, S-EL2 or EL3:
152 exception level is set to S-EL1.
568 load time (or EL1&0 Stage-1 for an S-EL1 SPMC). A memory region node can
572 EL1&0 Stage-1 for an S-EL1 SPMC) as peripherals and possibly allocate
583 non-secure EL1&0 Stage-2 table if it exists.
1042 secure EL1&0 Stage-1 translation.
1043 The EL1&0 Stage-2 translation hardware is fed by:
1045 - A secure IPA when the SP EL1&0 Stage-1 MMU is disabled.
1147 S-EL1 SPs managed by SPMC.
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| A D | secure-partition-manager-mm.rst | 43 privileged Exception Level (i.e. EL3 or S-EL1) makes security auditing of
127 Payload image executing at S-EL1 (e.g. a Trusted OS). Both are referred to as
265 A SVC causes an exception to be taken to S-EL1. TF-A assumes ownership of S-EL1
301 the Secure EL1&0 translation regime).
410 description and initialises the Secure EL1&0 translation regime as follows.
429 S-EL0 or S-EL1.
609 the Secure EL1&0 Translation regime with appropriate memory attributes.
701 region is equal to the Translation Granule size used in the Secure EL1&0
707 The caller must obtain the Translation Granule Size of the Secure EL1&0
733 of the Translation Granule Size used in the Secure EL1&0 translation
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| A D | el3-spmc.rst | 14 - Manages a single S-EL1 Secure Partition
16 - Provides support for EL3 Logical Partitions to support easy migration from EL3 to S-EL1.
23 and SPMC at EL3, one S-EL1 secure partition, with an optional
46 - BL32 option is re-purposed to specify the S-EL1 TEE or SP image.
159 exception-level = <0x2>; /* S-EL1 */
456 SPMC only supports a single Pinned MP S-EL1 SP. The *execution-ctx-count*
465 - SPMC is capable of forwarding Secure interrupt to S-EL1 SP
468 - Interrupt Number is not passed, S-EL1 SP can access the GIC registers directly.
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| A D | platform-interrupt-controller-API.rst | 153 Secure EL1 interrupts.
156 for Secure EL1 interrupts.
173 - ``INTR_TYPE_S_EL1``: interrupt is meant to be consumed by Secure EL1.
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| A D | exception-handling.rst | 147 - On GICv3 systems, when executing in S-EL1, pending Non-secure interrupts of
149 EL3. As a result, S-EL1 software cannot expect to handle Non-secure
150 interrupts at S-EL1. Essentially, this deprecates the routing mode described
153 In order for S-EL1 software to handle Non-secure interrupts while having
156 handled over to S-EL1.
489 to be taken to S-EL1 [#irq]_, so would get a chance to populate the designated
500 .. [#irq] In case of GICv2, Non-secure interrupts while in S-EL1 were signalled
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| A D | xlat-tables-lib-v2-design.rst | 80 the EL1&0 translation regime, the attributes also specify whether the region is
81 a User region (EL0) or Privileged region (EL1). See the ``MT_xxx`` definitions
82 in ``xlat_tables_v2.h``. Note that for the EL1&0 translation regime the Execute
83 Never attribute is set simultaneously for both EL1 and EL0.
127 create translation tables pertaining to the S-EL1&0 translation regime.
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| /arm-trusted-firmware-2.8.0/docs/plat/arm/fvp_r/ |
| A D | index.rst | 10 - MPU or MMU Support at EL0/EL1
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| /arm-trusted-firmware-2.8.0/services/std_svc/spm/el3_spmc/ |
| A D | spmc.h | 83 EL1 = 0, enumerator
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| /arm-trusted-firmware-2.8.0/docs/perf/ |
| A D | performance-monitoring-unit.rst | 79 - If set to ``0``, will increment the associated ``PMEVCNTR<n>`` at EL1.
85 Non-secure EL1.
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| /arm-trusted-firmware-2.8.0/docs/getting_started/ |
| A D | rt-svc-writers-guide.rst | 282 The PSCI and Test Secure-EL1 Payload Dispatcher services do not follow
302 Secure-EL1 Payload Dispatcher service (SPD)
306 or other Secure-EL1 Payload are special. These services need to manage the
307 Secure-EL1 context, provide the *Secure Monitor* functionality of switching
308 between the normal and secure worlds, deliver SMC Calls through to Secure-EL1
309 and generally manage the Secure-EL1 Payload through CPU power-state transitions.
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| A D | image-terminology.rst | 74 Secure-EL1 Payload (SP): ``AP_BL32``
78 normal world. However, it may refer to a more abstract Secure-EL1 Payload (SP).
80 single or primary image executing at Secure-EL1. In systems where there are
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| /arm-trusted-firmware-2.8.0/docs/design_documents/ |
| A D | context_mgmt_rework.rst | 49 Due to the way TF-A evolved, from EL3 interacting with an S-EL1 payload to
50 SPM in S-EL2, there is some code initializing S-EL1 registers which is
54 EL3 can do the bare minimal EL2 init and init EL1 to prepare for EL3 exit.
139 Note2: The EL1 context save and restore can possibly be removed when switching
140 to S-EL2 as SPM can take care of saving the incoming NS EL1 context.
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| /arm-trusted-firmware-2.8.0/docs/plat/ |
| A D | imx8m.rst | 99 causes those locations not to be filled, which in turn causing EL1&0 software
103 data exchange between EL3 and EL1&0 software.
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| /arm-trusted-firmware-2.8.0/docs/about/ |
| A D | features.rst | 40 - Secure Monitor library code such as world switching, EL1 context management
42 When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the
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| /arm-trusted-firmware-2.8.0/docs/process/ |
| A D | security.rst | 54 | |TFV-3| | RO memory is always executable at AArch64 Secure EL1 |
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| /arm-trusted-firmware-2.8.0/docs/plat/nxp/ |
| A D | nxp-layerscape.rst | 179 + EL1 BL32(Tee OS) | kernel
195 + EL1 fip-ddr BL32(Tee OS) | kernel
219 | Secure EL1 Payload Shared Memory (2 MB) |
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