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Searched refs:GENMASK (Results 1 – 25 of 48) sorted by relevance

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/arm-trusted-firmware-2.8.0/include/drivers/st/
A Dstm32mp13_rcc.h344 #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
348 #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
1745 #define RCC_IDR_ID_MASK GENMASK(31, 0)
1749 #define RCC_SIDR_SID_MASK GENMASK(31, 0)
1794 #define RCC_SELR_SRC_MASK GENMASK(2, 0)
1821 #define RCC_DIVR_DIV_MASK GENMASK(5, 0)
1825 #define RCC_APBXDIV_MASK GENMASK(2, 0)
1826 #define RCC_MPUDIV_MASK GENMASK(2, 0)
1827 #define RCC_AXIDIV_MASK GENMASK(2, 0)
1828 #define RCC_MLAHBDIV_MASK GENMASK(3, 0)
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A Dstm32_uart_regs.h43 #define USART_CR1_DEDT GENMASK(20, 16)
49 #define USART_CR1_DEAT GENMASK(25, 21)
72 #define USART_CR2_STOP GENMASK(13, 12)
82 #define USART_CR2_ABRMODE GENMASK(22, 21)
86 #define USART_CR2_ADD GENMASK(31, 24)
109 #define USART_CR3_WUS GENMASK(21, 20)
130 #define USART_GTPR_PSC GENMASK(7, 0)
131 #define USART_GTPR_GT GENMASK(15, 8)
134 #define USART_RTOR_RTO GENMASK(23, 0)
191 #define USART_RDR_RDR GENMASK(8, 0)
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A Dbsec2_reg.h15 #define DATA_LOWER_OTP_PERLOCK_MASK GENMASK(2, 0)
18 #define DATA_UPPER_OTP_PERLOCK_MASK GENMASK(3, 0)
62 #define BSEC_CONF_FRQ_MASK GENMASK(2, 1)
64 #define BSEC_CONF_PRG_WIDTH_MASK GENMASK(6, 3)
66 #define BSEC_CONF_TREAD_MASK GENMASK(8, 7)
83 #define BSEC_MODE_STATUS_MASK GENMASK(2, 0)
98 #define BSEC_DEN_ALL_MSK GENMASK(10, 0)
101 #define BSEC_FEN_ALL_MSK GENMASK(14, 0)
104 #define BSEC_IPVR_MSK GENMASK(7, 0)
A Dstm32mp15_rcc.h263 #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
282 #define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0)
492 #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
496 #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
504 #define RCC_RDLSICR_MRD_MASK GENMASK(20, 16)
2264 #define RCC_DIVR_DIV_MASK GENMASK(5, 0)
2268 #define RCC_APBXDIV_MASK GENMASK(2, 0)
2269 #define RCC_MPUDIV_MASK GENMASK(2, 0)
2270 #define RCC_AXIDIV_MASK GENMASK(2, 0)
2271 #define RCC_MCUDIV_MASK GENMASK(3, 0)
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A Dstm32_i2c.h23 #define I2C_CR1_DNF GENMASK(11, 8)
38 #define I2C_CR2_SADD GENMASK(9, 0)
46 #define I2C_CR2_NBYTES GENMASK(23, 16)
53 #define I2C_OAR1_OA1 GENMASK(9, 0)
58 #define I2C_OAR2_OA2 GENMASK(7, 1)
59 #define I2C_OAR2_OA2MSK GENMASK(10, 8)
63 #define I2C_OAR2_OA2MASK03 GENMASK(9, 8)
67 #define I2C_OAR2_OA2MASK07 GENMASK(10, 8)
71 #define I2C_TIMINGR_SCLL GENMASK(7, 0)
72 #define I2C_TIMINGR_SCLH GENMASK(15, 8)
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A Dstm32mp1_ddr_regs.h139 #define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)
143 #define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25)
158 #define DDRPHYC_PTR0_TDLLSRST_MASK GENMASK(5, 0)
160 #define DDRPHYC_PTR0_TDLLLOCK_MASK GENMASK(17, 6)
162 #define DDRPHYC_PTR0_TITMSRST_MASK GENMASK(21, 18)
166 #define DDRPHYC_ACIOCR_CKPDD_MASK GENMASK(10, 8)
168 #define DDRPHYC_ACIOCR_CKPDR_MASK GENMASK(13, 11)
170 #define DDRPHYC_ACIOCR_CSPDD_MASK GENMASK(21, 18)
178 #define DDRPHYC_DSGCR_CKEPDD_MASK GENMASK(19, 16)
180 #define DDRPHYC_DSGCR_ODTPDD_MASK GENMASK(23, 20)
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A Dstpmic1.h89 #define LDO_VOLTAGE_MASK GENMASK(6, 2)
90 #define BUCK_VOLTAGE_MASK GENMASK(7, 2)
97 #define LDO_BUCK_PULL_DOWN_MASK GENMASK(1, 0)
158 #define VINLOW_HYST_MASK GENMASK(1, 0)
160 #define VINLOW_THRESHOLD_MASK GENMASK(2, 0)
163 #define VINLOW_CTRL_REG_MASK GENMASK(7, 0)
A Dstm32mp_ddrctrl_regs.h192 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
198 #define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0)
201 #define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
211 #define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12)
221 #define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16)
229 #define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16)
232 #define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK GENMASK(31, 30)
245 #define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8)
246 #define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0)
/arm-trusted-firmware-2.8.0/include/drivers/
A Dmmc.h36 #define OCR_VDD_MIN_2V7 GENMASK(23, 15)
37 #define OCR_VDD_MIN_2V0 GENMASK(14, 8)
67 #define EXT_CSD_PART_CONFIG_ACC_MASK GENMASK(2, 0)
71 #define PART_CFG_BOOT_PART_EN_MASK GENMASK(5, 3)
94 #define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0)
95 #define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3)
125 #define SD_SWITCH_ALL_GROUPS_MASK GENMASK(23, 0)
/arm-trusted-firmware-2.8.0/plat/st/stm32mp1/
A Dstm32mp1_dbgmcu.c22 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
23 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
A Dstm32mp1_syscfg.c52 #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
54 #define SYSCFG_BOOTR_BOOTPD_MASK GENMASK(6, 4)
82 #define SYSCFG_CMPCR_RANSRC GENMASK(19, 16)
84 #define SYSCFG_CMPCR_RAPSRC GENMASK(23, 20)
116 #define SYSCFG_IDC_DEV_ID_MASK GENMASK(11, 0)
117 #define SYSCFG_IDC_REV_ID_MASK GENMASK(31, 16)
A Dstm32mp1_private.c20 #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16)
22 #define BOARD_ID_VARCPN_MASK GENMASK(15, 12)
24 #define BOARD_ID_REVISION_MASK GENMASK(11, 8)
26 #define BOARD_ID_VARFG_MASK GENMASK(7, 4)
28 #define BOARD_ID_BOM_MASK GENMASK(3, 0)
46 #define TAMP_BOOT_MODE_ITF_MASK GENMASK(15, 8)
48 #define TAMP_BOOT_MODE_AUTH_MASK GENMASK(23, 16)
57 #define TAMP_BOOT_FWU_INFO_IDX_MSK GENMASK(3, 0)
59 #define TAMP_BOOT_FWU_INFO_CNT_MSK GENMASK(7, 4)
/arm-trusted-firmware-2.8.0/drivers/st/usb/
A Dstm32mp1_usb.c67 #define OTG_DAINT_OUT_MASK GENMASK(31, 16)
69 #define OTG_DAINT_IN_MASK GENMASK(15, 0)
86 #define OTG_GUSBCFG_TRDT GENMASK(13, 10)
114 #define OTG_GRXSTSP_EPNUM GENMASK(3, 0)
115 #define OTG_GRXSTSP_BCNT GENMASK(14, 4)
117 #define OTG_GRXSTSP_PKTSTS GENMASK(20, 17)
127 #define OTG_GLPMCFG_BESL GENMASK(5, 2)
130 #define OTG_DCFG_DAD GENMASK(10, 4)
160 #define OTG_DIEPCTL_MPSIZ GENMASK(10, 0)
180 #define OTG_DIEPTSIZ_XFRSIZ GENMASK(18, 0)
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/arm-trusted-firmware-2.8.0/drivers/st/reset/
A Dstm32mp1_reset.c21 return ((reset_id & GENMASK(31, 5)) >> 5) * sizeof(uint32_t); in id2reg_offset()
26 return (uint8_t)(reset_id & GENMASK(4, 0)); in id2reg_bit_pos()
/arm-trusted-firmware-2.8.0/drivers/st/etzpc/
A Detzpc.c25 #define ETZPC_MODE_MASK GENMASK(1, 0)
27 #define ETZPC_ID_MASK GENMASK(7, 0)
38 #define ETZPC_DECPROT0_MASK GENMASK(1, 0)
74 #define PERIPH_ATTR_MASK GENMASK(2, 0)
/arm-trusted-firmware-2.8.0/drivers/allwinner/
A Dsunxi_msgbox.c26 #define FIFO_STAT_MASK GENMASK(0, 0)
29 #define MSG_STAT_MASK GENMASK(2, 0)
/arm-trusted-firmware-2.8.0/drivers/scmi-msg/
A Dclock.h28 #define SCMI_CLOCK_CLOCK_COUNT_MASK GENMASK(15, 0)
29 #define SCMI_CLOCK_MAX_PENDING_TRANSITIONS_MASK GENMASK(23, 16)
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/mcdi/
A Dmt_cpu_pm_cpc.c76 uint32_t cnt_mask = GENMASK(14, 0); in mtk_cpc_cluster_cnt_backup()
77 uint32_t clr_mask = GENMASK(1, 0); in mtk_cpc_cluster_cnt_backup()
191 val = GENMASK(1, 0); /* clr_mask */ in mtk_cpc_config()
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/mcdi/
A Dmt_cpu_pm_cpc.c76 uint32_t cnt_mask = GENMASK(14, 0); in mtk_cpc_cluster_cnt_backup()
77 uint32_t clr_mask = GENMASK(1, 0); in mtk_cpc_cluster_cnt_backup()
191 val = GENMASK(1, 0); /* clr_mask */ in mtk_cpc_config()
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/mcdi/
A Dmt_cpu_pm_cpc.c76 uint32_t cnt_mask = GENMASK(14, 0); in mtk_cpc_cluster_cnt_backup()
77 uint32_t clr_mask = GENMASK(1, 0); in mtk_cpc_cluster_cnt_backup()
191 val = GENMASK(1, 0); /* clr_mask */ in mtk_cpc_config()
/arm-trusted-firmware-2.8.0/plat/xilinx/versal_net/include/
A Dversal_net_def.h40 # define PLATFORM_MASK GENMASK(27U, 24U)
41 # define PLATFORM_VERSION_MASK GENMASK(31U, 28U)
/arm-trusted-firmware-2.8.0/include/lib/
A Dutils_def.h51 #define GENMASK GENMASK_64 macro
53 #define GENMASK GENMASK_32 macro
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/spmc/
A Dmtspmc_private.h137 #define CORE_SPMC_PWR_ON_ACK GENMASK(15, 0)
164 #define ILDO_RET_VOSEL GENMASK(7, 0)
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/spmc/
A Dmtspmc_private.h136 #define CORE_SPMC_PWR_ON_ACK GENMASK(11, 0)
163 #define ILDO_RET_VOSEL GENMASK(7, 0)
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/spmc/
A Dmtspmc_private.h129 #define CORE_SPMC_PWR_ON_ACK GENMASK(11, 0)
156 #define ILDO_RET_VOSEL GENMASK(7, 0)

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