1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef GICV2_H 9 #define GICV2_H 10 11 #include <drivers/arm/gic_common.h> 12 #include <platform_def.h> 13 14 /******************************************************************************* 15 * GICv2 miscellaneous definitions 16 ******************************************************************************/ 17 18 /* Interrupt group definitions */ 19 #define GICV2_INTR_GROUP0 U(0) 20 #define GICV2_INTR_GROUP1 U(1) 21 22 /* Interrupt IDs reported by the HPPIR and IAR registers */ 23 #define PENDING_G1_INTID U(1022) 24 25 /* GICv2 can only target up to 8 PEs */ 26 #define GICV2_MAX_TARGET_PE U(8) 27 28 /******************************************************************************* 29 * GICv2 specific Distributor interface register offsets and constants. 30 ******************************************************************************/ 31 #define GICD_ITARGETSR U(0x800) 32 #define GICD_SGIR U(0xF00) 33 #define GICD_CPENDSGIR U(0xF10) 34 #define GICD_SPENDSGIR U(0xF20) 35 36 /* 37 * Some GICv2 implementations violate the specification and have this register 38 * at a different address. Allow overriding it in platform_def.h as workaround. 39 */ 40 #ifndef GICD_PIDR2_GICV2 41 #define GICD_PIDR2_GICV2 U(0xFE8) 42 #endif 43 44 #define ITARGETSR_SHIFT 2 45 #define GIC_TARGET_CPU_MASK U(0xff) 46 47 #define CPENDSGIR_SHIFT 2 48 #define SPENDSGIR_SHIFT CPENDSGIR_SHIFT 49 50 #define SGIR_TGTLSTFLT_SHIFT 24 51 #define SGIR_TGTLSTFLT_MASK U(0x3) 52 #define SGIR_TGTLST_SHIFT 16 53 #define SGIR_TGTLST_MASK U(0xff) 54 #define SGIR_NSATT (U(0x1) << 16) 55 #define SGIR_INTID_MASK ULL(0xf) 56 57 #define SGIR_TGT_SPECIFIC U(0) 58 59 #define GICV2_SGIR_VALUE(tgt_lst_flt, tgt, nsatt, intid) \ 60 ((((tgt_lst_flt) & SGIR_TGTLSTFLT_MASK) << SGIR_TGTLSTFLT_SHIFT) | \ 61 (((tgt) & SGIR_TGTLST_MASK) << SGIR_TGTLST_SHIFT) | \ 62 ((nsatt) ? SGIR_NSATT : U(0)) | \ 63 ((intid) & SGIR_INTID_MASK)) 64 65 /******************************************************************************* 66 * GICv2 specific CPU interface register offsets and constants. 67 ******************************************************************************/ 68 /* Physical CPU Interface registers */ 69 #define GICC_CTLR U(0x0) 70 #define GICC_PMR U(0x4) 71 #define GICC_BPR U(0x8) 72 #define GICC_IAR U(0xC) 73 #define GICC_EOIR U(0x10) 74 #define GICC_RPR U(0x14) 75 #define GICC_HPPIR U(0x18) 76 #define GICC_AHPPIR U(0x28) 77 #define GICC_IIDR U(0xFC) 78 #define GICC_DIR U(0x1000) 79 #define GICC_PRIODROP GICC_EOIR 80 81 /* GICC_CTLR bit definitions */ 82 #define EOI_MODE_NS BIT_32(10) 83 #define EOI_MODE_S BIT_32(9) 84 #define IRQ_BYP_DIS_GRP1 BIT_32(8) 85 #define FIQ_BYP_DIS_GRP1 BIT_32(7) 86 #define IRQ_BYP_DIS_GRP0 BIT_32(6) 87 #define FIQ_BYP_DIS_GRP0 BIT_32(5) 88 #define CBPR BIT_32(4) 89 #define FIQ_EN_SHIFT 3 90 #define FIQ_EN_BIT BIT_32(FIQ_EN_SHIFT) 91 #define ACK_CTL BIT_32(2) 92 93 /* GICC_IIDR bit masks and shifts */ 94 #define GICC_IIDR_PID_SHIFT 20 95 #define GICC_IIDR_ARCH_SHIFT 16 96 #define GICC_IIDR_REV_SHIFT 12 97 #define GICC_IIDR_IMP_SHIFT 0 98 99 #define GICC_IIDR_PID_MASK U(0xfff) 100 #define GICC_IIDR_ARCH_MASK U(0xf) 101 #define GICC_IIDR_REV_MASK U(0xf) 102 #define GICC_IIDR_IMP_MASK U(0xfff) 103 104 /* HYP view virtual CPU Interface registers */ 105 #define GICH_CTL U(0x0) 106 #define GICH_VTR U(0x4) 107 #define GICH_ELRSR0 U(0x30) 108 #define GICH_ELRSR1 U(0x34) 109 #define GICH_APR0 U(0xF0) 110 #define GICH_LR_BASE U(0x100) 111 112 /* Virtual CPU Interface registers */ 113 #define GICV_CTL U(0x0) 114 #define GICV_PRIMASK U(0x4) 115 #define GICV_BP U(0x8) 116 #define GICV_INTACK U(0xC) 117 #define GICV_EOI U(0x10) 118 #define GICV_RUNNINGPRI U(0x14) 119 #define GICV_HIGHESTPEND U(0x18) 120 #define GICV_DEACTIVATE U(0x1000) 121 122 /* GICD_CTLR bit definitions */ 123 #define CTLR_ENABLE_G1_SHIFT 1 124 #define CTLR_ENABLE_G1_MASK U(0x1) 125 #define CTLR_ENABLE_G1_BIT BIT_32(CTLR_ENABLE_G1_SHIFT) 126 127 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ 128 #define INT_ID_MASK U(0x3ff) 129 130 #ifndef __ASSEMBLER__ 131 132 #include <cdefs.h> 133 #include <stdbool.h> 134 #include <stdint.h> 135 136 #include <common/interrupt_props.h> 137 138 /******************************************************************************* 139 * This structure describes some of the implementation defined attributes of 140 * the GICv2 IP. It is used by the platform port to specify these attributes 141 * in order to initialize the GICv2 driver. The attributes are described 142 * below. 143 * 144 * The 'gicd_base' field contains the base address of the Distributor interface 145 * programmer's view. 146 * 147 * The 'gicc_base' field contains the base address of the CPU Interface 148 * programmer's view. 149 * 150 * The 'target_masks' is a pointer to an array containing 'target_masks_num' 151 * elements. The GIC driver will populate the array with per-PE target mask to 152 * use to when targeting interrupts. 153 * 154 * The 'interrupt_props' field is a pointer to an array that enumerates secure 155 * interrupts and their properties. If this field is not NULL, both 156 * 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored. 157 * 158 * The 'interrupt_props_num' field contains the number of entries in the 159 * 'interrupt_props' array. If this field is non-zero, 'g0_interrupt_num' is 160 * ignored. 161 ******************************************************************************/ 162 typedef struct gicv2_driver_data { 163 uintptr_t gicd_base; 164 uintptr_t gicc_base; 165 unsigned int *target_masks; 166 unsigned int target_masks_num; 167 const interrupt_prop_t *interrupt_props; 168 unsigned int interrupt_props_num; 169 } gicv2_driver_data_t; 170 171 /******************************************************************************* 172 * Function prototypes 173 ******************************************************************************/ 174 void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data); 175 void gicv2_distif_init(void); 176 void gicv2_pcpu_distif_init(void); 177 void gicv2_cpuif_enable(void); 178 void gicv2_cpuif_disable(void); 179 unsigned int gicv2_is_fiq_enabled(void); 180 unsigned int gicv2_get_pending_interrupt_type(void); 181 unsigned int gicv2_get_pending_interrupt_id(void); 182 unsigned int gicv2_acknowledge_interrupt(void); 183 void gicv2_end_of_interrupt(unsigned int id); 184 unsigned int gicv2_get_interrupt_group(unsigned int id); 185 unsigned int gicv2_get_running_priority(void); 186 void gicv2_set_pe_target_mask(unsigned int proc_num); 187 unsigned int gicv2_get_interrupt_active(unsigned int id); 188 void gicv2_enable_interrupt(unsigned int id); 189 void gicv2_disable_interrupt(unsigned int id); 190 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority); 191 void gicv2_set_interrupt_type(unsigned int id, unsigned int type); 192 void gicv2_raise_sgi(int sgi_num, bool ns, int proc_num); 193 void gicv2_set_spi_routing(unsigned int id, int proc_num); 194 void gicv2_set_interrupt_pending(unsigned int id); 195 void gicv2_clear_interrupt_pending(unsigned int id); 196 unsigned int gicv2_set_pmr(unsigned int mask); 197 void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg); 198 199 #endif /* __ASSEMBLER__ */ 200 #endif /* GICV2_H */ 201