Searched refs:GPC_PU_PWRHSK (Results 1 – 8 of 8) sorted by relevance
| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/ |
| A D | dram_retention.c | 18 #define GPC_PU_PWRHSK (IMX_GPC_BASE + 0x01FC) macro
82 mmio_clrbits_32(GPC_PU_PWRHSK, BIT(1)); in dram_enter_retention()
83 while (mmio_read_32(GPC_PU_PWRHSK) & BIT(18)) { in dram_enter_retention()
86 mmio_setbits_32(GPC_PU_PWRHSK, BIT(1)); in dram_enter_retention()
89 mmio_clrbits_32(GPC_PU_PWRHSK, BIT(2)); in dram_enter_retention()
90 while (mmio_read_32(GPC_PU_PWRHSK) & BIT(20)) { in dram_enter_retention()
93 mmio_setbits_32(GPC_PU_PWRHSK, BIT(2)); in dram_enter_retention()
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| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mm/ |
| A D | gpc.c | 250 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
260 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU2D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
263 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU2D_ADB400_ACK)) { in imx_gpc_pm_domain_enable()
268 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU3D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
271 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU3D_ADB400_ACK)) { in imx_gpc_pm_domain_enable()
284 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU2D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
287 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU2D_ADB400_ACK)) { in imx_gpc_pm_domain_enable()
291 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU3D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
294 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU3D_ADB400_ACK)) { in imx_gpc_pm_domain_enable()
302 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
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| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mn/ |
| A D | gpc.c | 100 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
103 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) { in imx_gpc_pm_domain_enable()
118 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
121 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) { in imx_gpc_pm_domain_enable()
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| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mp/ |
| A D | gpc.c | 236 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
239 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) in imx_gpc_pm_domain_enable()
261 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
264 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) in imx_gpc_pm_domain_enable()
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| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mq/include/ |
| A D | gpc_reg.h | 24 #define GPC_PU_PWRHSK 0x1FC macro
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| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mn/include/ |
| A D | gpc_reg.h | 24 #define GPC_PU_PWRHSK 0x1FC macro
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| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mm/include/ |
| A D | gpc_reg.h | 24 #define GPC_PU_PWRHSK 0x1FC macro
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| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mp/include/ |
| A D | gpc_reg.h | 25 #define GPC_PU_PWRHSK 0x190 macro
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