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Searched refs:GPIO2_BASE (Results 1 – 11 of 11) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/rockchip/rk3328/drivers/pmu/
A Dpmu.c226 val = mmio_read_32(GPIO2_BASE + SWPORTA_DDR); in rockchip_soc_system_off()
228 mmio_write_32(GPIO2_BASE + SWPORTA_DDR, val); in rockchip_soc_system_off()
231 val = mmio_read_32(GPIO2_BASE); in rockchip_soc_system_off()
233 mmio_write_32(GPIO2_BASE, val); in rockchip_soc_system_off()
472 sram_data.pmic_sleep_gpio_save[1] = mmio_read_32(GPIO2_BASE + 4); in rk3328_pmic_suspend()
473 sram_data.pmic_sleep_gpio_save[0] = mmio_read_32(GPIO2_BASE); in rk3328_pmic_suspend()
475 mmio_write_32(GPIO2_BASE + 4, in rk3328_pmic_suspend()
477 mmio_write_32(GPIO2_BASE, in rk3328_pmic_suspend()
483 mmio_write_32(GPIO2_BASE, sram_data.pmic_sleep_gpio_save[0]); in rk3328_pmic_resume()
484 mmio_write_32(GPIO2_BASE + 4, sram_data.pmic_sleep_gpio_save[1]); in rk3328_pmic_resume()
/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey/include/
A Dhi6220.h58 #define GPIO2_BASE 0xF8013000 macro
/arm-trusted-firmware-2.8.0/plat/rockchip/rk3328/
A Drk3328_def.h45 #define GPIO2_BASE 0xff230000 macro
/arm-trusted-firmware-2.8.0/plat/rockchip/px30/
A Dpx30_def.h85 #define GPIO2_BASE 0xff260000 macro
/arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/include/shared/
A Daddressmap_shared.h40 #define GPIO2_BASE (MMIO_BASE + 0x07780000) macro
/arm-trusted-firmware-2.8.0/plat/rockchip/rk3328/drivers/soc/
A Dsoc.c36 MAP_REGION_FLAT(GPIO2_BASE, GPIO2_SIZE,
/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey/
A Dhikey_bl_common.c55 pl061_gpio_register(GPIO2_BASE, 2); in hikey_gpio_init()
/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey960/
A Dhikey960_bl_common.c449 pl061_gpio_register(GPIO2_BASE, 2); in hikey960_gpio_init()
/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey960/include/
A Dhi3660.h245 #define GPIO2_BASE UL(0xE8A0D000) macro
/arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/pmu/
A Dpmu.c937 gpio_direction[0] = mmio_read_32(GPIO2_BASE + 0x04); in suspend_apio()
975 mmio_clrbits_32(GPIO2_BASE + 0x04, 0x00001fff); in suspend_apio()
992 mmio_clrbits_32(GPIO2_BASE + 0x04, 0x1fff0000); in suspend_apio()
1048 mmio_write_32(GPIO2_BASE + 0x04, gpio_direction[0]); in resume_apio()
/arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/gpio/
A Drk3399_gpio.c95 .port_base = GPIO2_BASE,

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