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Searched refs:HPIPE_PWR_PLL_PHY_MODE_OFFSET (Results 1 – 3 of 3) sorted by relevance

/arm-trusted-firmware-2.8.0/drivers/marvell/
A Dcomphy.h54 #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 macro
56 (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
/arm-trusted-firmware-2.8.0/drivers/marvell/comphy/
A Dcomphy-cp110.h172 #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 macro
174 (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
A Dphy-comphy-cp110.c421 data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in mvebu_cp110_comphy_sata_power_on()
771 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
964 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1469 data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1832 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
2014 data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in mvebu_cp110_comphy_usb3_power_on()

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