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/arm-trusted-firmware-2.8.0/plat/nxp/common/soc_errata/
A Derrata.c15 INFO("SoC workaround for Errata A050426 was applied\n"); in soc_errata()
23 INFO("SoC workaround for Errata A009660 was applied\n"); in soc_errata()
27 INFO("SoC workaround for Errata A010539 was applied\n"); in soc_errata()
36 INFO("SoC workaround for DDR Errata A011396 was applied\n"); in soc_errata()
39 INFO("SoC workaround for DDR Errata A050450 was applied\n"); in soc_errata()
42 INFO("SoC workaround for DDR Errata A050958 was applied\n"); in soc_errata()
45 INFO("SoC workaround for DDR Errata A008511 was applied\n"); in soc_errata()
48 INFO("SoC workaround for DDR Errata A009803 was applied\n"); in soc_errata()
51 INFO("SoC workaround for DDR Errata A009942 was applied\n"); in soc_errata()
54 INFO("SoC workaround for DDR Errata A010165 was applied\n"); in soc_errata()
[all …]
/arm-trusted-firmware-2.8.0/lib/psa/
A Dmeasured_boot.c30 INFO("\t\t:"); in print_byte_array()
50 INFO("Measured boot extend measurement:\n"); in log_measurement()
51 INFO(" - slot : %u\n", index); in log_measurement()
52 INFO(" - signer_id :"); in log_measurement()
54 INFO(" - version : %s\n", version); in log_measurement()
55 INFO(" - version_size: %zu\n", version_size); in log_measurement()
56 INFO(" - sw_type : %s\n", sw_type); in log_measurement()
57 INFO(" - sw_type_size: %zu\n", sw_type_size); in log_measurement()
58 INFO(" - algorithm : %x\n", measurement_algo); in log_measurement()
59 INFO(" - measurement :"); in log_measurement()
[all …]
/arm-trusted-firmware-2.8.0/plat/brcm/board/stingray/src/
A Dscp_utils.c91 INFO("SCP Patch is already active.\n"); in plat_bcm_bl2_plat_handle_scp_bl2()
104 INFO("AP booted by Nitro\n"); in plat_bcm_bl2_plat_handle_scp_bl2()
120 INFO("MCU Patch Point: 0x%x\n", in plat_bcm_bl2_plat_handle_scp_bl2()
139 INFO("SCP Patch successfully initialized.\n"); in plat_bcm_bl2_plat_handle_scp_bl2()
144 INFO("SCP Patch version :0x%x\n", scp_patch_version); in plat_bcm_bl2_plat_handle_scp_bl2()
158 INFO("AVS voltages from cfg (including margin)\n"); in plat_bcm_bl2_plat_handle_scp_bl2()
160 INFO("%s\tVCORE: %dmv\n", in plat_bcm_bl2_plat_handle_scp_bl2()
164 INFO("%s\tIHOST03: %dmv\n", in plat_bcm_bl2_plat_handle_scp_bl2()
168 INFO("%s\tIHOST12: %dmv\n", in plat_bcm_bl2_plat_handle_scp_bl2()
172 INFO("AVS settings not applicable\n"); in plat_bcm_bl2_plat_handle_scp_bl2()
[all …]
A Dpm.c40 INFO("mpidr :%lu, cpuid:%d\n", mpidr, cpuid); in brcm_pwr_domain_on()
68 INFO("Cluster #%lu entering to snoop/dvm domain\n", cluster_id); in brcm_pwr_domain_on_finish()
78 INFO("Gic Initialization done for this affinity instance\n"); in brcm_pwr_domain_on_finish()
89 INFO("System rebooting - L%d...\n", reset_type); in brcm_system_reset()
101 INFO("System rebooting - L%d...\n", reset_type); in brcm_system_reset2()
A Dbl2_setup.c168 INFO("PCIE SATA Rescal Init done\n"); in brcm_stingray_pcie_reset()
345 INFO("Regulator supply got stable\n"); in set_swreg_based_on_otp()
432 INFO("DDR ref ID by SW (Not MCB Ref ID) 0x%x\n", in board_detect_fru()
438 INFO("**** FRU board information ****\n"); in board_detect_fru()
439 INFO("Language 0x%x\n", board_info.lang); in board_detect_fru()
440 INFO("Manufacturing Date %u.%02u.%02u, %02u:%02u\n", in board_detect_fru()
444 INFO("Manufacturer %s\n", board_info.manufacturer); in board_detect_fru()
445 INFO("Product Name %s\n", board_info.product_name); in board_detect_fru()
446 INFO("Serial number %s\n", board_info.serial_number); in board_detect_fru()
447 INFO("Part number %s\n", board_info.part_number); in board_detect_fru()
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/arm-trusted-firmware-2.8.0/plat/intel/soc/common/drivers/wdt/
A Dwatchdog.c22 INFO("Component Type : %x\r\n", mmio_read_32(WDT_COMP_VERSION)); in watchdog_info()
23 INFO("Component Version : %x\r\n", mmio_read_32(WDT_COMP_TYPE)); in watchdog_info()
30 INFO("Watchdog Timer is currently enabled\n"); in watchdog_status()
31 INFO("Current Counter : 0x%x\r\n", mmio_read_32(WDT_CCVR)); in watchdog_status()
33 INFO("Watchdog Timer is currently disabled\n"); in watchdog_status()
/arm-trusted-firmware-2.8.0/docs/plat/
A Dintel-stratix10.rst71 INFO: DDR: DRAM calibration success.
72 INFO: ECC is disabled.
73 INFO: Init HPS NOC's DDR Scheduler.
76 INFO: BL2: Doing platform setup
77 INFO: BL2: Loading image id 3
80 INFO: BL2: Loading image id 5
84 INFO: Entry point address = 0xffe1c000
85 INFO: SPSR = 0x3cd
88 INFO: ARM GICv2 driver initialized
92 INFO: Entry point address = 0x50000
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A Dintel-agilex.rst71 INFO: DDR: DRAM calibration success.
72 INFO: ECC is disabled.
75 INFO: BL2: Doing platform setup
77 INFO: Entry point address = 0xffe1c000
78 INFO: SPSR = 0x3cd
81 INFO: ARM GICv2 driver initialized
82 INFO: BL31: Initializing runtime services
84 INFO: BL31: Preparing for EL3 exit to normal world
85 INFO: Entry point address = 0x50000
86 INFO: SPSR = 0x3c9
A Dpoplar.rst122 INFO: BL1: RAM 0xe1000 - 0xe7000
123 INFO: BL1: Loading BL2
127 INFO: Entry point address = 0xe9000
128 INFO: SPSR = 0x3c5
131 INFO: BL2: Loading BL31
134 INFO: BL2: Loading BL33
138 INFO: Entry point address = 0x129000
139 INFO: SPSR = 0x3cd
143 INFO: BL31: Initializing runtime services
145 INFO: Entry point address = 0x37000000
[all …]
/arm-trusted-firmware-2.8.0/plat/brcm/board/stingray/driver/ext_sram_init/
A Dext_sram_init.c21 INFO(" - pnor pinmux init start.\n"); in brcm_stingray_pnor_pinmux_init()
160 INFO(" - pnor pinmux init done.\n"); in brcm_stingray_pnor_pinmux_init()
185 INFO(" - pnor sram init start.\n"); in brcm_stingray_pnor_sram_init()
188 INFO(" -- enable pnor clock\n"); in brcm_stingray_pnor_sram_init()
193 INFO(" -- reset pnor\n"); in brcm_stingray_pnor_sram_init()
233 INFO(" -- pnor set_cycles = 0x%x\n", val); in brcm_stingray_pnor_sram_init()
257 INFO(" -- pnor refresh_0 = 0x%x\n", val); in brcm_stingray_pnor_sram_init()
284 INFO(" - pnor sram init failed.\n"); in brcm_stingray_pnor_sram_init()
288 INFO(" - pnor sram init done.\n"); in brcm_stingray_pnor_sram_init()
295 INFO("%s start.\n", __func__); in ext_sram_init()
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/arm-trusted-firmware-2.8.0/bl32/tsp/
A Dtsp_main.c32 INFO("TSP: Total memory base : 0x%lx\n", (unsigned long) BL32_BASE); in tsp_main()
33 INFO("TSP: Total memory size : 0x%lx bytes\n", BL32_TOTAL_SIZE); in tsp_main()
48 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", in tsp_main()
73 INFO("TSP: cpu 0x%lx turned on\n", read_mpidr()); in tsp_cpu_on_main()
74 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", in tsp_cpu_on_main()
110 INFO("TSP: cpu 0x%lx off request\n", read_mpidr()); in tsp_cpu_off_main()
111 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n", in tsp_cpu_off_main()
149 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n", in tsp_cpu_suspend_main()
185 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu resume requests\n", in tsp_cpu_resume_main()
220 INFO("TSP: cpu 0x%lx received %s smc 0x%" PRIx64 "\n", read_mpidr(), in tsp_smc_handler()
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A Dtsp_ffa_main.c301 INFO("TSP: cpu 0x%lx off request\n", read_mpidr()); in tsp_cpu_off_main()
302 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n", in tsp_cpu_off_main()
442 INFO("TSP Tests: Memory Share Request--\n"); in handle_partition_message()
447 INFO("TSP Tests: Memory Lend Request--\n"); in handle_partition_message()
452 INFO("TSP Tests: Multi Endpoint Memory Share Request--\n"); in handle_partition_message()
457 INFO("TSP Tests: Multi Endpoint Memory Lend Request--\n"); in handle_partition_message()
461 INFO("TSP Tests: Relaying message--\n"); in handle_partition_message()
467 INFO("TSP Tests: echo message--\n"); in handle_partition_message()
472 INFO("TSP Tests: Unknown request ID %d--\n", (int) arg3); in handle_partition_message()
586 INFO("TSP FF-A endpoint id = 0x%x\n", tsp_id); in tsp_main()
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/arm-trusted-firmware-2.8.0/plat/arm/board/morello/
A Dmorello_bl2_setup.c67 INFO("Total DIMM size: %uGB\n", in dmc_ecc_setup()
73 INFO("Zeroing DDR memory range 0x80000000 - 0xFFFFFFFF\n"); in dmc_ecc_setup()
77 INFO("Zeroing DDR memory range 0x%llx - 0x%llx\n", in dmc_ecc_setup()
107 INFO("Configuring DMC Bing in client mode\n"); in dmc_ecc_setup()
131 INFO("C1 Tag Cache Enabled\n"); in dmc_ecc_setup()
137 INFO("C2 Tag Cache Enabled\n"); in dmc_ecc_setup()
154 INFO("Tag base set to 0x%lx\n", tag_mem_base); in dmc_ecc_setup()
157 INFO("Configuring DMC Bing in server mode\n"); in dmc_ecc_setup()
162 INFO("Enabling ECC on DMCs\n"); in dmc_ecc_setup()
/arm-trusted-firmware-2.8.0/plat/st/stm32mp1/
A Dbl2_plat_setup.c60 INFO("Reset reason (0x%x):\n", rstsr); in print_reset_reason()
64 INFO("System exits from STANDBY\n"); in print_reset_reason()
69 INFO("MPU exits from CSTANDBY\n"); in print_reset_reason()
75 INFO(" Power-on Reset (rst_por)\n"); in print_reset_reason()
80 INFO(" Brownout Reset (rst_bor)\n"); in print_reset_reason()
106 INFO(" IWDG1 Reset (rst_iwdg1)\n"); in print_reset_reason()
111 INFO(" IWDG2 Reset (rst_iwdg2)\n"); in print_reset_reason()
116 INFO(" MPU Processor 0 Reset\n"); in print_reset_reason()
122 INFO(" MPU Processor 1 Reset\n"); in print_reset_reason()
128 INFO(" Pad Reset from NRST\n"); in print_reset_reason()
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/arm-trusted-firmware-2.8.0/plat/mediatek/lib/system_reset/
A Dreset_cros.c21 INFO("MTK System Reset\n"); in mtk_system_reset_cros()
32 INFO("MTK System Off\n"); in mtk_system_off_cros()
50 INFO("Reset init\n"); in lib_reset_ctrl_init()
/arm-trusted-firmware-2.8.0/lib/optee/
A Doptee_utils.c154 INFO("OPTEE ep=0x%x\n", (unsigned int)header_ep->pc); in parse_optee_header()
155 INFO("OPTEE header info:\n"); in parse_optee_header()
156 INFO(" magic=0x%x\n", header->magic); in parse_optee_header()
157 INFO(" version=0x%x\n", header->version); in parse_optee_header()
158 INFO(" arch=0x%x\n", header->arch); in parse_optee_header()
159 INFO(" flags=0x%x\n", header->flags); in parse_optee_header()
160 INFO(" nb_images=0x%x\n", header->nb_images); in parse_optee_header()
180 INFO("Invalid OPTEE header, set legacy mode.\n"); in parse_optee_header()
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/apusys/
A Dmtk_apusys.c19 INFO("[APUSYS] ops=0x%x\n", request_ops); in apusys_kernel_ctrl()
45 INFO("[APUSYS] reviser_ctxt=%x,%x\n", in apusys_kernel_ctrl()
48 INFO("[APUSYS]fw=0x%08x,boot=0x%08x,def=0x%08x,sys=0x%08x\n", in apusys_kernel_ctrl()
58 INFO("[APUSYS] md32_boot_ctrl=0x%08x,runstall=0x%08x\n", in apusys_kernel_ctrl()
/arm-trusted-firmware-2.8.0/plat/nxp/common/warm_reset/
A Dplat_warm_reset.c37 INFO("Not a SW(Warm) triggered reset.\n"); in is_warm_boot()
44 INFO("Warm Reset was triggered..\n"); in is_warm_boot()
46 INFO("Warm Reset was not triggered..\n"); in is_warm_boot()
112 INFO("Doing DDR Self refresh.\n"); in prep_n_execute_warm_reset()
/arm-trusted-firmware-2.8.0/plat/brcm/board/common/
A Dboard_arm_trusted_boot.c73 INFO("NOT AB\n"); in plat_is_trusted_boot()
77 INFO("AB\n"); in plat_is_trusted_boot()
207 INFO("NON-AB: Do not read DAUTH!\n"); in plat_get_rotpk_info()
215 INFO("readKeys (DAUTH) from BL11\n"); in plat_get_rotpk_info()
239 INFO("AB DEV: FAST AUTH!\n"); in plat_get_rotpk_info()
251 INFO("sotp_read_key (DAUTH): %i\n", ret); in plat_get_rotpk_info()
273 INFO("Use internal key hash.\n"); in plat_get_rotpk_info()
280 INFO("No hash found in SOTP\n"); in plat_get_rotpk_info()
397 INFO("CTR %i\n", nvctr); in sotp_get_trusted_nvctr()
447 INFO("NCTR %i\n", nvctr); in sotp_get_nontrusted_nvctr()
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/arm-trusted-firmware-2.8.0/bl31/
A Dbl31_main.c145 INFO("BL31: Initialising Exception Handling Framework\n"); in bl31_main()
150 INFO("BL31: Initializing runtime services\n"); in bl31_main()
170 INFO("BL31: Initializing BL32\n"); in bl31_main()
185 INFO("BL31: Initializing RMM\n"); in bl31_main()
258 INFO("BL31: Preparing for EL3 exit to %s world\n", in bl31_prepare_next_image_entry()
/arm-trusted-firmware-2.8.0/drivers/brcm/
A Dchimp.c95 INFO("Waiting for ChiMP handshake...\n"); in bcm_chimp_wait_handshake()
113 INFO("Got handshake from ChiMP!\n"); in bcm_chimp_wait_handshake()
220 INFO("Setting fastboot type %d entry to 0x%x\n", mode, fb_entry); in bcm_chimp_set_fastboot()
243 INFO("Transferring %d byte(s) from 0x%lx to 0x%lx\n", in bcm_chimp_load_fw_from_spi()
251 INFO("Transferred %d byte(s) from 0x%lx to 0x%lx (%lu%%)\n", in bcm_chimp_load_fw_from_spi()
318 INFO("Found chimp firmware at 0x%lx, size %lu byte(s)\n", in bcm_chimp_find_fw_in_spi()
376 INFO("Loading ChiMP firmware, addr 0x%lx, size %lu byte(s)\n", in bcm_chimp_initiate_fastboot()
385 INFO("Skip ChiMP QSPI fastboot type %d due to sideload requested\n", in bcm_chimp_initiate_fastboot()
389 INFO("Instruct ChiMP to fastboot\n"); in bcm_chimp_initiate_fastboot()
391 INFO("Fastboot mode set\n"); in bcm_chimp_initiate_fastboot()
/arm-trusted-firmware-2.8.0/drivers/marvell/
A Dcache_llc.c94 INFO("Enabling LLC\n"); in llc_runtime_enable()
166 INFO("=== LLC SRAM WRITE test %s\n", msg); in llc_sram_test()
172 INFO("=== LLC SRAM WRITE test %s PASSED\n", msg); in llc_sram_test()
173 INFO("=== LLC SRAM READ test %s\n", msg); in llc_sram_test()
179 INFO("=== LLC SRAM READ test %s FAILED @ 0x%08lx)\n", in llc_sram_test()
184 INFO("=== LLC SRAM READ test %s PASSED (last read = 0x%08x)\n", in llc_sram_test()
/arm-trusted-firmware-2.8.0/drivers/brcm/i2c/
A Di2c.c141 INFO("SMB_CFG_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
144 INFO("SMB_TIMGCFG_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
147 INFO("SMB_ADDR_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
153 INFO("SMB_SLVFIFOCTL_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
159 INFO("SMB_MSTRCMD_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
162 INFO("SMB_SLVCMD_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
165 INFO("SMB_EVTEN_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
168 INFO("SMB_EVTSTS_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
177 INFO("SMB_SLVDATAWR_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
180 INFO("SMB_SLVDATARD_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
[all …]
/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey/
A Dhisi_mcu.c153 INFO("%s: AO_SC_SYS_CTRL2=%x\n", __func__, in hisi_mcu_start_run()
190 INFO("%s: mcu sections %d:\n", __func__, i); in hisi_mcu_load_image()
191 INFO("%s: src = 0x%x\n", in hisi_mcu_load_image()
193 INFO("%s: dst = 0x%x\n", in hisi_mcu_load_image()
195 INFO("%s: size = %d\n", __func__, head->secs[i].size); in hisi_mcu_load_image()
197 INFO("%s: [SRC 0x%x] 0x%x 0x%x 0x%x 0x%x\n", in hisi_mcu_load_image()
200 INFO("%s: [DST 0x%x] 0x%x 0x%x 0x%x 0x%x\n", in hisi_mcu_load_image()
/arm-trusted-firmware-2.8.0/plat/mediatek/common/
A Dmtk_smc_handlers.c100 INFO("print smc descriptor pool\n"); in print_smc_descriptor()
104 INFO("descriptor name:%s\n", p_smc_desc->smc_name); in print_smc_descriptor()
105 INFO("descriptor index:%d\n", *p_smc_desc->smc_descriptor_index); in print_smc_descriptor()
106 INFO("smc id 32:0x%x, smc id 64:0x%x\n", in print_smc_descriptor()
152 INFO("BL33 SMC ID:0x%x not supported\n", smc_id); in mtk_smc_handler_bl33()
175 INFO("NSEL1 SMC ID:0x%x not supported\n", smc_id); in mtk_smc_handler_nsel1()
211 INFO("Secure SMC ID:0x%x not supported\n", smc_id); in mtk_smc_handler()
223 INFO("SMC ID:0x%x not supported\n", smc_id); in mtk_smc_handler()

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