| /arm-trusted-firmware-2.8.0/plat/mediatek/drivers/mcusys/v1/ |
| A D | mcucfg.h | 19 #define MP2_CPUCFG (MCUCFG_BASE + 0x2208)
21 #define MP0_CPUTOP_SPMC_CTL (MCUCFG_BASE + 0x788)
22 #define MP1_CPUTOP_SPMC_CTL (MCUCFG_BASE + 0x78C)
89 #define SPARK2LDO (MCUCFG_BASE + 0x2700)
92 #define MP0_AXI_CONFIG (MCUCFG_BASE + 0x02C)
101 #define MP0_RW_RSVD0 (MCUCFG_BASE + 0x06C)
103 #define MP1_AXI_CONFIG (MCUCFG_BASE + 0x22C)
117 #define MP0_SPMC (MCUCFG_BASE + 0x788)
118 #define MP1_SPMC (MCUCFG_BASE + 0x78C)
139 #define CPUSYS0_SPARKEN (MCUCFG_BASE+0x1c04)
[all …]
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| /arm-trusted-firmware-2.8.0/plat/mediatek/drivers/cpu_pm/cpcv3_2/ |
| A D | mt_cpu_pm.h | 80 #define DREQ20_BIG_VPROC_ISO (MCUCFG_BASE + 0xad8c)
83 #define CORE_RVBRADDR_0_0_L (MCUCFG_BASE + 0xc900)
84 #define CORE_RVBRADDR_0_1_L (MCUCFG_BASE + 0xc908)
85 #define CORE_RVBRADDR_0_2_L (MCUCFG_BASE + 0xc910)
86 #define CORE_RVBRADDR_0_3_L (MCUCFG_BASE + 0xc918)
87 #define CORE_RVBRADDR_0_4_L (MCUCFG_BASE + 0xc920)
88 #define CORE_RVBRADDR_0_5_L (MCUCFG_BASE + 0xc928)
89 #define CORE_RVBRADDR_0_6_L (MCUCFG_BASE + 0xc930)
90 #define CORE_RVBRADDR_0_7_L (MCUCFG_BASE + 0xc938)
91 #define MCUCFG_MP0_CLUSTER_CFG5 (MCUCFG_BASE + 0xc8e4)
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| A D | mt_smp.h | 13 #define CPU_PWR_STATUS (MCUCFG_BASE + 0xA840)
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8183/drivers/spmc/ |
| A D | mtspmc_private.h | 154 #define MCUCFG_CPUSYS0_SPARKVRETCNTRL (MCUCFG_BASE + 0x1c00)
162 #define MCUCFG_CPUSYS0_CPU0_SPMC_CTL (MCUCFG_BASE + 0x1c30)
163 #define MCUCFG_CPUSYS0_CPU1_SPMC_CTL (MCUCFG_BASE + 0x1c34)
164 #define MCUCFG_CPUSYS0_CPU2_SPMC_CTL (MCUCFG_BASE + 0x1c38)
165 #define MCUCFG_CPUSYS0_CPU3_SPMC_CTL (MCUCFG_BASE + 0x1c3c)
171 #define MCUCFG_MP2_BASE (MCUCFG_BASE + 0x2000)
185 #define MCUCFG_MP0_SPMC (MCUCFG_BASE + 0x788)
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8183/include/ |
| A D | platform_def.h | 25 #define MCUCFG_BASE 0x0c530000 macro
83 #define MT_L2_WRITE_ACCESS_RATE (MCUCFG_BASE + 0x604)
84 #define MP0_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f0)
85 #define MP1_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f4)
86 #define EMI_WFIFO (MCUCFG_BASE + 0x0b5c)
122 #define INT_POL_CTL0 (MCUCFG_BASE + 0xa80)
123 #define SEC_POL_CTL_EN0 (MCUCFG_BASE + 0xa00)
124 #define GIC_SYNC_DCM (MCUCFG_BASE + 0x758)
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| A D | mt_gic_v3.h | 12 #define GIC_INT_MASK (MCUCFG_BASE + 0x5e8)
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| A D | plat_dcm.h | 10 #define MP2_SYNC_DCM (MCUCFG_BASE + 0x2274)
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/dcm/ |
| A D | mtk_dcm_utils.h | 16 #define MP_CPUSYS_TOP_BASE (MCUCFG_BASE + 0x8000)
17 #define CPCCFG_REG_BASE (MCUCFG_BASE + 0xA800)
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| /arm-trusted-firmware-2.8.0/plat/mediatek/drivers/dcm/mt8188/ |
| A D | mtk_dcm_utils.h | 16 #define MP_CPUSYS_TOP_BASE (MCUCFG_BASE + 0x8000)
17 #define CPCCFG_REG_BASE (MCUCFG_BASE + 0xA800)
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/dcm/ |
| A D | mtk_dcm_utils.h | 16 #define MP_CPUSYS_TOP_BASE (MCUCFG_BASE + 0x8000)
17 #define CPCCFG_REG_BASE (MCUCFG_BASE + 0xA800)
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| /arm-trusted-firmware-2.8.0/plat/mediatek/drivers/mcusys/ |
| A D | mcusys.c | 12 MAP_REGION_FLAT(MCUCFG_BASE, MCUCFG_REG_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/dfd/ |
| A D | plat_dfd.h | 22 #define MCU_BIU_BASE (MCUCFG_BASE)
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8183/drivers/mcsi/ |
| A D | mcsi.h | 86 #define CCI_CLK_CTRL (MCUCFG_BASE + 0x660)
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/dfd/ |
| A D | plat_dfd.h | 22 #define MCU_BIU_BASE (MCUCFG_BASE)
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| /arm-trusted-firmware-2.8.0/plat/mediatek/drivers/dfd/mt8188/ |
| A D | plat_dfd.h | 26 #define MCU_BIU_BASE (MCUCFG_BASE)
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/dfd/ |
| A D | plat_dfd.h | 29 #define MCU_BIU_BASE (MCUCFG_BASE)
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/include/ |
| A D | platform_def.h | 15 #define MCUCFG_BASE 0x0c530000 macro
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/include/ |
| A D | platform_def.h | 13 #define MCUCFG_BASE (0x0C530000) macro
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8173/include/ |
| A D | mt8173_def.h | 26 #define MCUCFG_BASE (IO_PHYS + 0x200000) macro
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| A D | mcucfg.h | 104 static struct mt8173_mcucfg_regs *const mt8173_mcucfg = (void *)MCUCFG_BASE;
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/include/ |
| A D | platform_def.h | 14 #define MCUCFG_BASE (0x0C530000) macro
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8188/include/ |
| A D | platform_def.h | 15 #define MCUCFG_BASE (0x0C530000) macro
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/spmc/ |
| A D | mtspmc_private.h | 33 #define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs))
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/spmc/ |
| A D | mtspmc_private.h | 33 #define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs))
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/spmc/ |
| A D | mtspmc_private.h | 31 #define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs))
|