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Searched refs:MCU_BIU_BASE (Results 1 – 5 of 5) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/mediatek/drivers/dfd/mt8188/
A Dplat_dfd.h26 #define MCU_BIU_BASE (MCUCFG_BASE) macro
27 #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040)
50 #define DFD_V35_ENABLE (MCU_BIU_BASE + 0xE0A8)
51 #define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xE0AC)
52 #define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xE0B0)
53 #define DFD_V35_CTL (MCU_BIU_BASE + 0xE0B4)
54 #define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xE0C0)
55 #define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xE0C4)
56 #define DFD_V50_GROUP_0_63_DIFF (MCU_BIU_BASE + 0xE2AC)
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/dfd/
A Dplat_dfd.h29 #define MCU_BIU_BASE (MCUCFG_BASE) macro
30 #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040)
53 #define DFD_V35_ENABLE (MCU_BIU_BASE + 0xE0A8)
54 #define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xE0AC)
55 #define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xE0B0)
56 #define DFD_V35_CTL (MCU_BIU_BASE + 0xE0B4)
57 #define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xE0C0)
58 #define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xE0C4)
59 #define DFD_V50_GROUP_0_63_DIFF (MCU_BIU_BASE + 0xE2AC)
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/dfd/
A Dplat_dfd.h22 #define MCU_BIU_BASE (MCUCFG_BASE) macro
23 #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040)
44 #define DFD_V35_ENALBE (MCU_BIU_BASE + 0xE0A8)
45 #define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xE0AC)
46 #define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xE0B0)
47 #define DFD_V35_CTL (MCU_BIU_BASE + 0xE0B4)
48 #define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xE0C0)
49 #define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xE0C4)
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/dfd/
A Dplat_dfd.h22 #define MCU_BIU_BASE (MCUCFG_BASE) macro
23 #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xA040)
37 #define DFD_V35_ENALBE (MCU_BIU_BASE + 0xA0A8)
38 #define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xA0AC)
39 #define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xA0B0)
40 #define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xA0C0)
41 #define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xA0C4)
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8183/include/
A Dplat_debug.h13 #define MCU_BIU_BASE 0x0c530000 macro
16 #define DFD_INTERNAL_CTL (MCU_BIU_BASE + MISC1_CFG_BASE + 0x00)
17 #define CA15M_DBG_CONTROL (MCU_BIU_BASE + CA15M_CFG_BASE + 0x728)
18 #define CA15M_PWR_RST_CTL (MCU_BIU_BASE + CA15M_CFG_BASE + 0x08)

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