Searched refs:MISC1_CFG_BASE (Results 1 – 9 of 9) sorted by relevance
27 #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040) macro28 #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)30 #define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)32 #define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C)39 #define DFD_V30_CTL (MISC1_CFG_BASE + 0x48)41 #define DFD_POWER_CTL (MISC1_CFG_BASE + 0x50)42 #define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58)43 #define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C)45 #define DFD_TEST_SI_2 (MISC1_CFG_BASE + 0x1D8)46 #define DFD_TEST_SI_3 (MISC1_CFG_BASE + 0x1DC)[all …]
30 #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040) macro31 #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)33 #define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)35 #define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C)42 #define DFD_V30_CTL (MISC1_CFG_BASE + 0x48)44 #define DFD_POWER_CTL (MISC1_CFG_BASE + 0x50)45 #define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58)46 #define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C)48 #define DFD_TEST_SI_2 (MISC1_CFG_BASE + 0x1D8)49 #define DFD_TEST_SI_3 (MISC1_CFG_BASE + 0x1DC)[all …]
141 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()147 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
23 #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040) macro24 #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)26 #define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)28 #define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C)29 #define DFD_CHAIN_LENGTH2 (MISC1_CFG_BASE + 0x20)34 #define DFD_V30_CTL (MISC1_CFG_BASE + 0x48)36 #define DFD_POWER_CTL (MISC1_CFG_BASE + 0x50)37 #define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58)38 #define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C)40 #define DFD_TEST_SI_2 (MISC1_CFG_BASE + 0x1D8)[all …]
124 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()130 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
23 #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xA040) macro25 #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)26 #define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08)27 #define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)28 #define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10)29 #define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28)31 #define DFD_V30_CTL (MISC1_CFG_BASE + 0x48)32 #define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C)33 #define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58)34 #define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C)[all …]
83 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()89 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
14 #define MISC1_CFG_BASE 0xb00 macro16 #define DFD_INTERNAL_CTL (MCU_BIU_BASE + MISC1_CFG_BASE + 0x00)
27 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()33 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
Completed in 9 milliseconds