| /arm-trusted-firmware-2.8.0/plat/hisilicon/poplar/ |
| A D | plat_pm.c | 76 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in poplar_pwr_domain_on_finish()
120 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in poplar_validate_power_state()
122 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in poplar_validate_power_state()
147 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in poplar_get_sys_suspend_power_state()
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| /arm-trusted-firmware-2.8.0/plat/hisilicon/hikey/ |
| A D | hikey_pm.c | 24 ((state)->pwr_domain_state[MPIDR_AFFLVL0])
167 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in hikey_get_sys_suspend_power_state()
232 if (pwr_lvl != MPIDR_AFFLVL0) in hikey_validate_power_state()
235 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in hikey_validate_power_state()
238 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in hikey_validate_power_state()
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| /arm-trusted-firmware-2.8.0/plat/imx/common/ |
| A D | imx8_psci.c | 43 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
58 for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) in imx_get_sys_suspend_power_state()
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| /arm-trusted-firmware-2.8.0/plat/renesas/common/ |
| A D | plat_pm.c | 37 #define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0])
259 if (pwr_lvl != MPIDR_AFFLVL0) in rcar_validate_power_state()
262 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in rcar_validate_power_state()
264 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in rcar_validate_power_state()
283 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in rcar_get_sys_suspend_power_state()
290 for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) in rcar_get_sys_suspend_power_state()
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| /arm-trusted-firmware-2.8.0/plat/hisilicon/hikey960/ |
| A D | hikey960_pm.c | 27 ((state)->pwr_domain_state[MPIDR_AFFLVL0])
156 if (pwr_lvl != MPIDR_AFFLVL0) in hikey960_validate_power_state()
159 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in hikey960_validate_power_state()
162 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in hikey960_validate_power_state()
293 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in hikey960_get_sys_suspend_power_state()
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| /arm-trusted-firmware-2.8.0/plat/qemu/qemu_sbsa/ |
| A D | sbsa_pm.c | 62 MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
65 MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),
183 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in qemu_pwr_domain_on_finish()
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| /arm-trusted-firmware-2.8.0/plat/rockchip/common/ |
| A D | plat_pm.c | 22 ((state)->pwr_domain_state[MPIDR_AFFLVL0])
150 if (pwr_lvl != MPIDR_AFFLVL0) in rockchip_validate_power_state()
153 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in rockchip_validate_power_state()
156 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in rockchip_validate_power_state()
176 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in rockchip_get_sys_suspend_power_state()
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| /arm-trusted-firmware-2.8.0/plat/qemu/common/ |
| A D | qemu_pm.c | 55 MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
58 MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),
186 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in qemu_pwr_domain_on_finish()
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| /arm-trusted-firmware-2.8.0/plat/brcm/board/stingray/src/ |
| A D | brcm_pm_ops.c | 29 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
362 if (pwr_lvl != MPIDR_AFFLVL0) in brcm_validate_power_state()
365 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in brcm_validate_power_state()
368 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in brcm_validate_power_state()
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| A D | pm.c | 63 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in brcm_pwr_domain_on_finish()
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| /arm-trusted-firmware-2.8.0/plat/rpi/common/ |
| A D | rpi3_pm.c | 53 MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
56 MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),
159 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in rpi3_pwr_domain_on_finish()
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| /arm-trusted-firmware-2.8.0/plat/amlogic/axg/ |
| A D | axg_pm.c | 102 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in axg_pwr_domain_on_finish()
117 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in axg_pwr_domain_off()
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| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/ |
| A D | imx8m_psci.h | 10 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
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| /arm-trusted-firmware-2.8.0/plat/imx/imx8qm/include/ |
| A D | platform_def.h | 26 #define IMX_PWR_LVL0 MPIDR_AFFLVL0
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| /arm-trusted-firmware-2.8.0/plat/xilinx/versal/ |
| A D | plat_psci.c | 202 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal_validate_power_state()
204 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in versal_validate_power_state()
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| /arm-trusted-firmware-2.8.0/plat/xilinx/zynqmp/ |
| A D | plat_psci.c | 185 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in zynqmp_validate_power_state()
187 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in zynqmp_validate_power_state()
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| /arm-trusted-firmware-2.8.0/plat/xilinx/versal_net/ |
| A D | plat_psci_pm.c | 204 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal_net_validate_power_state()
206 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in versal_net_validate_power_state()
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| /arm-trusted-firmware-2.8.0/plat/qti/sc7180/inc/ |
| A D | platform_def.h | 31 #define QTI_PWR_LVL0 MPIDR_AFFLVL0
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| /arm-trusted-firmware-2.8.0/plat/qti/sc7280/inc/ |
| A D | platform_def.h | 31 #define QTI_PWR_LVL0 MPIDR_AFFLVL0
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| /arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t210/ |
| A D | plat_psci_handlers.c | 55 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; in tegra_soc_validate_power_state()
64 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN; in tegra_soc_validate_power_state()
81 for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) in tegra_soc_validate_power_state()
201 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; in tegra_soc_pwr_domain_suspend()
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| /arm-trusted-firmware-2.8.0/plat/ti/k3/common/ |
| A D | k3_psci.c | 20 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
265 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { in k3_get_sys_suspend_power_state()
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| /arm-trusted-firmware-2.8.0/include/plat/marvell/armada/a3k/common/ |
| A D | marvell_def.h | 35 #define MARVELL_PWR_LVL0 MPIDR_AFFLVL0
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| /arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t186/ |
| A D | plat_psci_handlers.c | 81 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; in tegra_soc_validate_power_state()
113 stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & in tegra_soc_pwr_domain_suspend()
373 uint8_t stateid_afflvl0 = target_state->pwr_domain_state[MPIDR_AFFLVL0]; in tegra_soc_pwr_domain_on_finish()
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| /arm-trusted-firmware-2.8.0/include/plat/marvell/armada/a8k/common/ |
| A D | marvell_def.h | 32 #define MARVELL_PWR_LVL0 MPIDR_AFFLVL0
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| /arm-trusted-firmware-2.8.0/plat/imx/imx8qx/ |
| A D | imx8qx_psci.c | 116 if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL0])) { in imx_domain_suspend()
206 if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL0])) { in imx_domain_suspend_finish()
|